LX2160a processor DDR configuration in ATF source code

[Nikhiln]

Hi,

I'm trying to bring up a custom LX2160a based SBC board. I'm getting initial BL2 prints, and DDR initialization is failing. What are the things I have to modify for DDR initialization?

I'm using 4GB DDR4 memory on each controller with x32 bit data width. My application is data rate of 2600MTps. What are the things I have to modify for these settings to work?

I'm flashing bl2_flexspi_nor.pbl and fip_uboot.bin files only. Do I need to flash any other images for DDR to initialize and boot the processor properly.

Below is the UART log I'm getting.

NOTICE:  BL2: v2.4(release):LSDK-21.08-0-g340b20bcb-dirty
NOTICE:  BL2: Built : 08:36:13, Jul 23 2024
ERROR:   Invalid DIMM combination.
ERROR:   Parsing DIMM Error
ERROR:   DDR init failed.
NOTICE:  Incorrect DRAM0 size is defined in platform_def.h

[June_Lu]

"DDR init failed" has already been resolved. Please kindly create a new thread to continue to discuss BL31 issue. BL31 is another complex topic.
Thanks

[June_Lu]

Have the value of phy_vref been optimized? you can use the QCVS tool to find the optimized value of the phy_vref, only select "Auto search and detect for DDR VREF start value” then run the test first.

[Nikhiln]

Hi,

There is an update in the case. I was able to change the DDR configuration from "DIMM to fixed DDR on board", also I have changed some of the default ddr parameters with the help of CodeWarrior QCVS DDRv tool. Now "DDR init failed" error is not there. It is getting stuck at BL31 phase. Latest UART log is also attached.

Also, while running QCVS DDRv tool VREF training is passed, but all the other tests are failing. What is the reason it is getting stuck at this phase? How to proceed further?

// uart log from processor
NOTICE: BL2: v2.4(release):LSDK-21.08-0-g340b20bcb-dirty
NOTICE: BL2: Built : 07:26:43, Aug 3 2024
NOTICE: Fixed DDR on board
NOTICE: DDR PMU Hardware version-0x1210
NOTICE: DDR PMU Firmware vision-0x1001 (vA-2019.04)
NOTICE: DDR4 UDIMM with 1-rank 32-bit bus (x16)

NOTICE: 16 GB DDR4, 32-bit, CL=12, ECC off
NOTICE: BL2: Booting BL31
NOTICE: BL31: v2.4(release):LSDK-21.08-0-g340b20bcb-dirty
NOTICE: BL31: Built : 07:26:43, Aug 3 2024
NOTICE: Welcome to lx2160ardb BL31 Phase
// end of uart log

[Nikhiln]

I am not able to find an option only to enable: "Auto search and detect for DDR VREF start value". But when the test is run it is only doing the VREF search test and error is coming as given in the previously shared logs in the attachment.

How to get DDR firmware image to flash in the following location: 0x00800000. While building image using, it is not building the new fip_ddr_all.bin (settings modified for our board in atf source file: plat/nxp/soc-lx2160 is not reflecting in this binary).

Also is this binary file required to be flashed for running QCVS tool.

[June_Lu]

Need to confirm all the information and investigate the issue, will update it later.

[June_Lu]

Would you kindly share the  SBC board.

LX2160ARDB is a recommended reference for the LX2160A reference design board provides design and evaluation of the LX2160A or LX2162A processors.

https://www.nxp.com/design/design-center/software/qoriq-developer-resources/layerscape-lx2160a-refer...

It is possible that the issue is caused by improper operation of the DRAM memory.

Have you used CodeWarrior QCVS DDR Tool to validate the DRAM operation?

QCVS_DDR_User_Guide

Thanks

[Nikhiln]

We have referred LX2160ARDB files for our design. Also, for schematic and layout we followed recommendation in "AN5407_Design checklist" and "AN5097_DDR layout guide".

Attaching the SBC board schematic for your reference.

In BL2 UART log I shared it is saying DIMM configuration, we are discrete ICs on our board. Where I have to change these settings?

It is possible that the issue is caused by improper operation of the DRAM memory.

>>> Also, MRST from the processor is not driven high from processor. We have used the same DDR memory with other devices it is working so I doubt the issue related to DRAM memory.

Have you used CodeWarrior QCVS DDR Tool to validate the DRAM operation?

>>> Yes, I tried running CodeWarrior QCVS DDR Tool validation in default settings with only different data width and frequency of operation. error log of the tests is attached. Tried multiple validation as tests available in QCVS tool. In all the tests error is Firmware has failed.

During the QCVS DDRv tool validation test MRST was going high.

My doubt is configuration issue. Where can I find the configuration setting while building the images using LSDK 21.08?

1. Operational DDR tests: Write-read-compare

2. Centering the clock: Auto search and detect for DDR VREF start value

3. Read ODT and Driver: Read ODT and Driver

[Nikhiln]

Any update on the same?