LX2160A - PCIe 4GB BAR

[rulamp]

Platform: LX2160ARDB Rev 1
LSDK: 19.04 and 20.12
Also working with both LSDK versions and a vanilla u-boot build with the proper changes to the .dtsi

I am trying to increase the PCIe BAR size to 4GB. No matter what I have tried, I have not been able to figure it out.

I have been making changes to the PCIe 5 entry in 'packages/firmware/u-boot/arch/arm/dts/fsl-lx2160a.dtsi' 

I have tried many different values for the ranges field and according to this post following should work:

	pcie5: pcie@3800000 {
		compatible = "fsl,lx2160a-pcie";
		reg = <0x00 0x03800000 0x0 0x80000   /* PAB registers */
		       0x00 0x03880000 0x0 0x40000   /* LUT registers */
		       0x00 0x038c0000 0x0 0x40000   /* PF control registers */
		       0xa0 0x00000000 0x0 0x2000>; /* configuration space */
		reg-names = "ccsr", "lut", "pf_ctrl", "config";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		bus-range = <0x0 0xff>;
		ranges = <0x81000000 0x0 0x00000000 0xa0 0x00020000 0x0 0x00010000   /* downstream I/O */
			  0x82000000 0x1 0x00000000 0xa0 0x00000000 0x1 0x00000000>; /* non-prefetchable memory */
	};

 But it does not. I would also expect either 

0x82000000 0x1 0x00000000 0xa1 0x00000000 0x1 0x00000000>; /* non-prefetchable memory */

or

0x83000000 0x1 0x00000000 0xa1 0x00000000 0x1 0x00000000>; /* non-prefetchable memory */

To work as well, but I get the following error on boot:

PCIe5: pcie@3800000 Root Complex: x4 gen3
PCI: Failed autoconfig bar 10
PCI: Failed autoconfig bar 18

 And trying to access md a100000000 shows all 0xFFs.
Some of the other values I have tried resulted in:

"Synchronous Abort" handler, esr 0x96000021
elr: 000000008207cab4 lr : 000000008207ca08 (reloc)
elr: 00000000fbda2ab4 lr : 00000000fbda2a08
x0 : 000000000000000b x1 : 00000000fffffffc
x2 : 00000000fbb1ef0a x3 : 0000000000000020
x4 : 00000000fffffffd x5 : 00000000fbb1ec88
x6 : 0000000000000066 x7 : 00000000fbb1ee40
x8 : 0000000000000000 x9 : 0000000000000008
x10: 00000000000186a0 x11: 00000000ffffffd8
x12: 0000000000000010 x13: 000000000001869f
x14: 00000000fbb1f280 x15: 0000000000000021
x16: 00000000fbd3a658 x17: 0000000000000000
x18: 00000000fbb21da0 x19: 0000000000000004
x20: 0000000000000004 x21: 0000000000000004
x22: 000000a0ffffffff x23: 00000000fbb1ef0b
x24: 0000000000000000 x25: 00000000fbb1eea8
x26: 00000000fbdbf1df x27: 0000000000000008
x28: 0000000000000004 x29: 00000000fbb1ee40

Code: 2a0403f3 17ffffcc 7100129f 54000181 (b94002c3)
Resetting CPU ...

Any help to get a 4GB BAR working would be greatly appreciated.

Edit 1:
When trying to read the iATU registers (0x3800900 - 0x3800920) by writing to the index register, the result is always 00s. This applies to both (non-working) 4GB BAR dtsi values and (working) 2GB BAR dtsi values.

=> mw.b 3800900 0
=> md.l 3800900 40
03800900: 00000000 00000000 00000000 00000000  ................
03800910: 00000000 00000000 00000000 00000000  ................
03800920: 00000000 00000000 00000000 00000000  ................

Edit 2:
I got 4GB to work with the following values in fsl-lx2160a.dtsi

0x83000000 0x0 0x00000000 0xa2 0x00000000 0x1 0x00000000>;

This seems to allow a total of 4GB for the sum of space that all BARs of the EP connected to PCIe5. need However, looking at the memory map (page 43 of the QorIQ LX2162A Reference Manual) it seems there should be a total of 32GB available.
I believe that changing CONFIG_SYS_PCI_MEMORY_SIZE of ../packages/firmware/u-boot/drivers/pci/pcie_layerscape.h to 8GB or 16GB or maybe 32GB should allow the use of the total 32GB size as specified in the ref man, but I am not sure.

So how do I go about using the total 32GB that is available?
Also, I understand needing to match sizes with the next valid address, but why must we start at

0xa0 + SIZE

 ? It wastes so much of the available space when working with large BAR sizes.

[yipingwang]

On Layerscape platforms, you should not do the configuration like this. CCSR is in 1G low memory space, DDR memory space is from 2G, these memory space should not be overlapped with PCIe outbound Windows, otherwise transactions of EP accessing these memory space will be dropped.

non-prefetchable memory only has 32bit memory space, it doesn't work to configure as the above. Why do you need so large non-prefetchable memory space?

If using EP BAR is prefetchable, you could use a 1:1 memory mapped prefetchable range, modify the entry as the following.

0xc3000000 0x1 0x00000000 0xa1 0x00000000 0x1 0x00000000>; /* 4GB prefetchable memory */

[rulamp]

Thanks for the response.
Even though you say that it won't work, I can confirm that the following works:

0x83000000 0x0 0x00000000 0xa1 0x00000000 0x1 0x00000000>;

 While your suggestion of the following does NOT:

0xc3000000 0x1 0x00000000 0xa1 0x00000000 0x1 0x00000000>;

 
I can even get 8GB BAR to work with the following:

0x83000000 0x0 0x00000000 0xa2 0x00000000 0x2 0x00000000>;

Why would this be?