LS1046A Watchdog Register not set

[imurillo_s]

Hello,

I have a simmilar problem to https://community.nxp.com/t5/Layerscape/LS1046A-watchdog-timeout/m-p/1552553#M11398 but I do not find usefull the solution provided there.

I am trying to use the WD over uboot, just to check its functionality.When I activate the watchdog, It reset our board but the WDOGx_WRSR register does not change (its status is 0010h after WD reset). The commands that I use in uboot are:

mw.b 0x2A70000 0x4 1

mw.b 0x2A70001 0x34 1

## the board resets after the 2.5s

md.b 0x2A70004 2

## the output is 0010h

I have check with the HW departement and the RESET_REQ_B assertion properly handled.

Also, if I set [SRS] bit in WCR register, I could not see the [SFTW] bit in WRSR register as set.

Thank you very much.

[scottwelsh]

Hello imurillo_s,
Did you receive a response to your question? I am experiencing the exact behavior you describe. That is, if the watchdog WT in WDOG1_WCR times out, upon LS1046A reset, the WDOG1_WRSR register does NOT indicate the reset was due to watchdog timeout via the TOUT bit, bit 14. Bit 14 should be a 1 but it is not. That is, the WDOG1_WRSR register shows value 0x0010 (reserved bit 11 is high). Further, register RSTRQSR1 should show a 1 for bit 22, the CORE_WDOG1_RST_RR field to indicate, "Core watchdog reset request from WDOG1 is active." Register RSTRQSR1 instead shows 0x00004000. That is, the MBEE_RR bit is a 1.

Next, if I cause a hardware reset due to software reset request via setting the active low SRS bit (bit 11 to 0), where value 0 is "Assert wdog_rst_b to COP". The system does reset but upon starting back up, I do NOT see bit SFTW (bit 15) of WDOG1_WRSR set to 1. The WDOG1_WRSR register is 0x0010.