LS1028ARDB-PA difference between CPLD firmware Rev. 6 and Rev. 8

[rbaur]

Is there any information/changelog about CPLD firmware?

We found out, a before posted issue about GPIO1_DAT25 irq line behaviour depends on CPLD firmware version. With rev. 6 of firmware the posted solution works fine, with currently shipped version rev. 8 not. With rev. 8 we can't get any irq on line GPIO1_DAT25.

Flashing back to rev 6 works for irq issue, but we don't know what other issues or function were changed or fixed with rev 8.

Using mikroBUS INT Pin (GPIO1_DAT25) as trigger for gpiod based application on LS128ARDB-PA 

[ufedor]

Please refer to the attached Release Notes for the CPLD V8.

[rbaur]

fedor,

i assume CTL[5] ist ment to be "general control" register of QIXIS configuration.

Is it possible to configure bit 5 during bootup to enable the PIC e.g. patching the QIXIS init inside uboot?

What about the registers for:

POLARITY
EDGE/LEVEL
MASK
STAT

Where can i configure/read them?

[rbaur]

fedor,
thanks a lot for your quick response. The release notes are very helpful!
One thing i need to know about [E30]

Which configuration do i have to do for activating the PIC?
What does CTL[5] mean? is it part of BRDCFG (QIXIS) or part of RCW?

[ufedor]

> What does CTL[5] mean?

Please refer to the QorIQ LS1028A Reference Design Board Reference Manual, Rev. 2, 3.10 General Control (CTL).