I am writing ENETC support for a bare-bones project (LS1028A). I am using u-boot fsl_enetc.c as an example. Whenever I try to transmit the controller seems to not acknowledge the packet.
I have rechecked my code that was based on the u-boot fsl_enetc.c file. I don’t see anything I am missing. When I transmit, the enetc controller doesn’t seem to process the buffer descriptor I present to it.
FYI, the RCW I am using are the same as the NXP dev board values. Here are my initialization steps:
- I issue an PCIe FLR by writing 0x8000 to 0x1F0000048 (PCI_CFC_PCIE_DEV_CTL). I wait 100 msec.
- I set 0x1F0000004 (PCI_CFH_CMD) to 0x406.
- I set SGMIIACR1 to 0x800 to enable SGMII on the SERDES.
- I initialize the SGMII interface using the MDIO registers (PM0_MDIO_CFG, PM0_MDIO_CTL, and PM0_MDIO_DATA). This was based on the u-boot code. I verified the writes are working by reading the values back.
- I setup the MAC address using PSI0PMAR0 and PSI0MAR1.
- I setup the RX and TX BDR count both to one using PSI0CFGR0.
- I set the max packet frame size to 1536 using PM0_MAXFRM.
- I enable the MAC port by writing 0x8813 to PM0_COMMAND_CONFIG. This is the same value used in u-boot.
- I enable the port by writing a 0x10000 to PMR.
- I write a 0x30303030 to SICAR0. The value is different from u-boot because the MMU and cache are not enabled.
- I enable the station interface by writing a 0x80000000 to SIMR.
To setup the TX buffer descriptors I followed the u-boot code. I made sure the descriptors are 128 byte aligned. I printed out the contents of the descriptor and everything seems ok. However when I increment TB0PIR, I never see TB0CIR change. It is as if the controller isn’t started.
I am not using the MMU or cache with this code. I do not know if that is an issue.
I am not using a PCIe driver to discover the Ethernet controller since the addresses and capabilities are hardcoded.
Any suggestions why I can’t transmit would be helpful.
