Hello,
We are designing a custom board based on a LS1023A with 2GB DDR4 + ECC (one bank).
We plan to connect and use this DDR memory with a 16-bit data bus witdh.
It seems to be OK by adjusting DDR_SDRAM_CFG[DBW] to '10b' as mentioned in the Reference Manual.
However, it is not clearly noted which data bus lanes we must use in this case : MDQ[15..0] or MDQ[31..16] ?
Regards,
Samuel
Solved! Go to Solution.
if the DDR_SDRAM_CFG[DBW] = 2'b10 for 16-bit data bus configuration, the MDQ [0:15] will be used.
if the DDR_SDRAM_CFG[DBW] = 2'b01 for 32-bit data bus configuration, the MDQ [0:31] will be used.
if the DDR_SDRAM_CFG[DBW] = 2'b10 for 16-bit data bus configuration, the MDQ [0:15] will be used.
if the DDR_SDRAM_CFG[DBW] = 2'b01 for 32-bit data bus configuration, the MDQ [0:31] will be used.
The DDR data assignment of the bus data is proposed into document Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces, Rev. 2, 07/2019 page 4 Table 1. DDR4 design checklist (continued).
Route all signals within a given byte lane on the same critical layer with the same via
count. Assuming ECC is used, the DDR4 data bus consists of nine data byte lanes.
NOTE: The byte ordering below is not a requirement; byte lanes can be routed in the
order that best fits the customer design.
To facilitate fan-out of the DDR4 data lanes (if needed), alternate adjacent data lanes
onto different critical layers (see Figure 1 and Figure 2).
NOTE: Some product implementations may only implement a 32-bit wide interface.
NOTE: If the device supports ECC, NXP highly recommends that the user implements
ECC on the initial hardware prototypes.
Additional information is proposed o application note QorIQ LS1043A Design Checklist , Rev. 6, 02/2021 page 18 in the note section.