LS1021 core freez on outbound pcie read

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LS1021 core freez on outbound pcie read

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ivanpetrov
Contributor II

Hello.

We have our custom LS1021 board (running Linux) connected via PCIe link with an endpoint device. Data transfers work fine in general but there are problems in one particular situation. Any outbound non-posted read request from RC (LS1021) to EP freezes the cpu core (which issued the request) if the PCIe link is down or goes down (simulated by reseting the EP in our case). If and when the link comes back up, LS core unfreezes and continues to execute code. Our issue seems to be related with the ones in this unresolved topic https://community.nxp.com/message/856380.

We have the following questions:

1. Is it an expected behavior from the PCIe block of LS1021?

2. Is the completion timeout mechanism implemented in LS1021? Is it possible to generate an interrupt when it is detected?

3. How can we handle and recover from a "stuck" read request to a link in a down state?

4. What is the purpose of the "reserved" IRQ lines numbered 177(209) and 178(210) in the kernel/Documentation/devicetree/bindings/pci/layerscape-pci.txt file?

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2 Replies

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shahabal
Contributor I

Hi there,

Did you find any solution for this?

We also face similar issue that Linux freezes after a few hours to a few days period. Our CPU target is LS1020 and the PCIe EP is FPGA.

We first thought that the issue may be in our kernel drivers, but after debugging everything the Linux freezing is still persisting. Now we think that maybe the source of the problem is in hardware but not quite sure.

Any advice is appreciated!

SH_A

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yipingwang
NXP TechSupport
NXP TechSupport

Please refer to the section "PCI Express Uncorrectable Error Case Study - Completion Timeout" section in the document https://www.nxp.com/webapp/sps/download/preDownload.jsp?render=true.

You could enable  "PCIe Advanced Error Reporting" driver in Linux Kernel for the Error detection.

Bus options --->
[*] PCI Express support
[*] Root Port Advanced Error Reporting support

For details, please refer to "PCIe Advanced Error Reporting User Manual" in SDK 2.0 user manual.

Please refer to the driver code in drivers/pci/pcie/aer/.


Have a great day,
TIC

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