LS1021 SPI reception with eDMA

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LS1021 SPI reception with eDMA

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pratapgaikwad
Contributor I

I am trying to use SPI with eDMA. The SPI transmission with eDMA is working properly, but I am facing issue with SPI reception with eDMA. Please see below details on issue:

eDMA is not able to transfer content from SPI RX FIFO to destination RAM location properly. After the trigger from SPI RX FIFO Drain event, DMA transaction gets completed but SPI RX FIFO pointer does not change regularly after each DMA read operation on SPI POPR register

 

Following configuration is used:

  1. SPI Configuration for RX DMA transfer: 
    • Enable RX FIFO Drain DMA triggering in RSER register.
  2. eDMA channel configuration:
    • Source Port Size: 32 bit
    • Major loop count: Total number of 32bit-words to be transferred
    • Source Address: Address of SPI POPR register
    • Destination offset: 4 
    • Source offset: 0
    • Destination Address: Address of RAM buffer
    • NBYTES (Minor loop): 4 bytes
    • Destination port Size: 32 bit
    • Used DMA channel number: 1
  3. DMA MUX configuration
    • Channel 1 Trigger source -> SPI RFDF
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Pavel
NXP TechSupport
NXP TechSupport

Check your eDMA configuration. See Application Note for eDMA using in the attachment.


Have a great day,
Pavel Chubakov

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pratapgaikwad
Contributor I

Thanks for sharing application note on eDMA. I read the applicatiion note and also verified my eDMA configuration. You can see the eDMA configuration I made in original question. I am currently also using eDMA with other peripherals of LS1021A (like LPUART), and it works very well without any issue. I am facing the issue only with SPI and eDMA combination (SPI reception with eDMA to be specific).  DMA performs complete transfer as specified by eDMA configuration, but the "SPI RX FIFO pointer" does not change regularly after each DMA read operation on "SPI POPR" register.  This results in stale values transfered by DMA (because RX FIFO pointer does not change).

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