LS1043ARDB-PA/PB

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LS1043ARDB-PA/PB

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trondwang
Contributor I

Hello,

the evaluation board for LS1043 has a separate power (U17) that gives the 1.2V voltage called +TVDD. Why is this power needed? The PMIC (U33) on the board has already a 1.2V output called +GVDD. Could I remove U17 and connect +TDD on the CPU to +GVDD? We will not need AQR105 (U9).

reg.

Trond Inge

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r8070z
NXP TechSupport
NXP TechSupport

Have a great day,

Yes the PMIC has default start-up sequence for the different SW and LDO.
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trondwang
Contributor I

Thank you for help!

With respect to the LS1043 MDIO voltage, I see from the circuit diagram that the 2.5V will be available before GVDD from the PMIC, so correct power-on sequence will be  maintained in this case.

But if 1.8V (from SW2 on the PMIC) is connected, how will then correct power-on sequence be maintained because GVDD comes also comes from the PMIC ? Is this secured internally in the PMIC VR500V4?

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r8070z
NXP TechSupport
NXP TechSupport

Have a great day,

Yes the PMIC has default start-up sequence for the different SW and LDO.
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r8070z
NXP TechSupport
NXP TechSupport

Have a great day,

This power is needed for the Ehternet Phy and LS1043A MDIO which control that Phy. GVDD belongs to DDR system. During the power-on sequence the TVDD should be applied before the GVDD. If you do not need for the MDIO at 1.2V you can connect the TVDD pin to the 1.8V or 2.5V power line.

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