DDR compatability of LS1046A and LS1043A

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DDR compatability of LS1046A and LS1043A

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jvfausto
Contributor I

We are trying to use a PCB originally created with a LS1043A CPU to bring up a LS1046A CPU. The BGA map for the LS1043A DDR pins has equivalents in the LS1046A, but there is a swap in the lanes.

Board name:   LS1043 LS1046

Lane number: 0           8(ECC)

                       1           3

                       2           2

                       3           1

Is there a way to change the settings in the DDR component of the CodeWarrior IDE to represent the change in pinout for the 32-bit bus?

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377件の閲覧回数
Hector_Villarruel
NXP TechSupport
NXP TechSupport

Hello @jvfausto 

Regarding your question:

Is there a way to change the settings in the DDR component of the CodeWarrior IDE to represent the change in pinout for the 32-bit bus?

Regarding your specific configuration, it is not possible, since the configurations are set to 0 to 7 , you can find the available configurations at the Codewarrior DDR component on the "DQ mapping controller pin".

Please find attached on the case an image in reference.

DDR_DQMapping.png

 Have a great day.

BR,

Hector Villarruel

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378件の閲覧回数
Hector_Villarruel
NXP TechSupport
NXP TechSupport

Hello @jvfausto 

Regarding your question:

Is there a way to change the settings in the DDR component of the CodeWarrior IDE to represent the change in pinout for the 32-bit bus?

Regarding your specific configuration, it is not possible, since the configurations are set to 0 to 7 , you can find the available configurations at the Codewarrior DDR component on the "DQ mapping controller pin".

Please find attached on the case an image in reference.

DDR_DQMapping.png

 Have a great day.

BR,

Hector Villarruel

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Hector_Villarruel
NXP TechSupport
NXP TechSupport

Hello @jvfausto 

Hope this post finds you well,

This email is to inform you that we acknowledge the receipt of your case,
I Keep working on the solution on this case.
I’ll keep you informed on the process,

Have a great day.