Content originally posted in LPCWare by jharwood on Sun Apr 24 12:02:55 MST 2011
Quote: paksoft
Thanks for your explanation, and how about TFE(TNF) and RNE(RFF) of SSP1SR? I'm really new to ARM architecture.
Regards,
pak
FIFO = First In First Out, also known as a queue
From the manual:
Quote:
- 8 frame FIFOs for both transmit and receive.
Quote:
TFE Transmit FIFO Empty. This bit is 1 is[I](sic)[/I] the Transmit FIFO is empty, 0 if not.
TNF Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not
RNE Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.
RFF Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not
So, if TFE == 1 you can send data, if TNF == 1 you can send more data .. and more .. and more.. until TNF becomes 0.
You may then want to see what came back, if RFF == 1 then there are eight frames waiting and the SSP could be dropping incoming frames **
You keep reading frames from the Rx FIFO while RNE == 1
Also, read the explanation given in the SSPn Data Register
** See SSPn RIS or MIS interrupt status register, ROR = receive overrun
Quote:
RORRIS This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is
overwritten by the new frame data when this occurs.
