i2s: MCLK signal

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i2s: MCLK signal

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Contributor II

Hi, I set up a DMA to transfer data over I2S.0 in my lpc4337. Alsignals look OK (SCK, WS and SD), but the MCLK signal is only 1v, and it does NOT look square at all.

This is the output of a 20Mhz the oscilloscope I have at home:

500mV x 0.2uS

IMG_20190407_002822736.jpg

mclk signal is about 5mm of distance from the board pin and it can't get any closer. I used to have a protoboard with a lot of long cables, and the signal looked like the one below, but that's no longer the case.

MCLK and SCK with very long cables on a protoboard. 1V x 0.2uS.

Ignore this picture as this is no longer a problem.

IMG_20190404_194505364.jpg

Any tips on what may be going on?

I2S extra question

CS4335 protocol is i2s, left justified, MSB first. From their datasheet the data is valid on the first rising edge.

About shifting the bits with respect to frame edges. I believe this is called PCM typical format, while NOT shifting the bits is the typical i2s protocol. Out of curiosity, is there any way to do this in the LPC4337? And about being left justified, is there any way to set it up? Because I've been reading the Datasheet but I'm not able to find it.

So far I had to modify LPC open to change to big endianess, and enable MCLK, which was not possible with the existing examples.

Nevertheless the main issue for now is that I'm not being able to output a clean MCLK to power on the CS4335 as it requires MCLK and WS to power ON. (SCK is optional).

Thank you.

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NXP TechSupport
NXP TechSupport

Hi, Emilio,

Yes, the LPC4337 supports the standard I2S mode(Bits are right shifted by one with respect to frame edges), I also checked the data sheet of CS4334-5-8-9-F7.pdf, the Figure 10. CS4334 Data Format (I²S) means that only CS4334 supports the standard I2S mode.

Hope it can help you

BR

Xiangjun Rong

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NXP TechSupport
NXP TechSupport

Hi, Emilio,

Regarding the question that "the MCLK signal is only 1v, and it does NOT look square at all.", it appears that the Oscilloscope bad pass-band leads to the issue for example distort and low voltage, maybe the original signal is okay. If possible, can you use another digital oscilloscope to have a test?

I have downloaded the data sheet of CS4335, the codec supports both modes: Frame signal with one-bit shift early or frame signal without one-bit shift early modes. Pls refer to Figure 10. CS4334 Data Format (I²S) and Figure 11. CS4335 Data Format in DS of CS4335. For the LPC4337, I think it only supports the standard I2S mode that the Frame signal is of one-bit shift early.

Hope it can help you

BR

XiangJun Rong

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Contributor II

Hi, thanks for the reply. I will assume my oscilloscope is not showing the right voltage for such high frequencies.

With that in mind, I can see two things:

1) Looking at the logic analyzer I can confirm the LPC 4337 sends the data in i2s standard format. Bits are right shifted by one with respect to frame edges

2) Only the CS4334 supports standard i2s format(shifted). The CS4335 expects the bits in PCM standard format (not shifted).

Since there is no way for the LPC4337 to output data in PCM standard format (I didn't find it in the User Manual UM10503), I can conclude it's compatible with the CS4334, but NOT with the CS4335.

Is this correct?

Thank you,

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NXP TechSupport
NXP TechSupport

Hi, Emilio,

Yes, the LPC4337 supports the standard I2S mode(Bits are right shifted by one with respect to frame edges), I also checked the data sheet of CS4334-5-8-9-F7.pdf, the Figure 10. CS4334 Data Format (I²S) means that only CS4334 supports the standard I2S mode.

Hope it can help you

BR

Xiangjun Rong

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Contributor II

I will change the DAC then.

Thank you.

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