Flexcomm's SPI only supports SSEL0, SSEL1. Datasheet description says up to 4 SSs, except FC3 & FC4 the SS pins exist only SSEL0, SSEL1 in chip package.
So, I am testing using GPIO to selecting over 4 SPI devices.
First of all, I use lpcxpresso54608_freertos_spi example to see exactly how Master-slave communicates. (Attached Figure 1)
In this code, you changed the SSEL0 setting to GPIO, adding GPIO control before and after communication.
The master->slave communication is displayed normally.
In slave->master communication, the first byte is added as a pile of 0xFF.
(Attached Figure 2)
Perhaps, it's because GPIO CS occurs before the clock. Is there any way to modify it?
(Note, I attach the code to test GPIO_CS "_with_gpio.zip".)
(and also I attach the console log of GPIO_CS).
Hi toipaz
Your Figure 2. No data missing on MISO. just one data later comparing with Figure 1.
I think the problem is not due to SPI master fill the first as FF, but slave send data issue.
Please check your SPI slave code, monitoring with scope, when receive first data from master, what does it send out?
Jun Zhang
Thanks for your reply.
When I test it over and over again,
Slave's first transfer data is not the first data I want to send, but the data that was previously in Buffer.
Whenever the communication by Master resumes, if I want to start transmission on Slave, the first byte is "data left in previous FIFO." (attach file: GPIO_log.txt)
The repeat test is performed accurately in synchronization with code using SSELn. (attach file: SSELn_log.txt)
With GPIO CS, the first transmission from Slave is "previously FIFO(?) data."
As you can see by comparing the two codes, only GPIO CS was added to the Master in the basic structure...
I don't know what I did wrong, so I ask you.
in the case of using GPIO simulate CS, you need make sure the slave transmission buffer the right data before sending.
On slave side, I suggest you dummy read spi right after slave spi initialization to clear the transmission buffer then write the valid data to it.