Smart card interface. Changing OSR(/etu/clk-per-bit) after PPS.

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Smart card interface. Changing OSR(/etu/clk-per-bit) after PPS.

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by kabikov on Fri May 30 08:10:26 MST 2014
Hi!

I'm developing smart card reader with lpc11u14. Now I'm trying to change speed of sc interface. After sending&recieving PPS I'm try to change USART parametrs. When I stay with F/D = 372 (example PPS1=0x32 : 8MHz, F = 744, D = 2) and warm reset after it it's all ok. But when I try to use some F/D other then 372 (PPS1=0x94 for example 5MHz, F = 512, D = with reset I got strange ATR like "E0 E0 FF FF E0 E0 00 FF E0 00 1F 00 00 00 00 00 FC 00". I look at signals with logic analyzer between sc and lpc and it seems good ATR after reset.

* All PPS is successful
* Card is support this bitrate by documentation too
* Code for programing USART:
* If it's not restarting after PPS there is no reaction on any command

#define _BV(_x_) (1UL << (_x_))
void SetupSmartcardInterface(uint32_t f_max, uint32_t clock_in_etu, uint32_t etu_divider, int databits,
int parity, int guardbits, int retries) {
system_clock_divider = (SystemCoreClock + f_max - 1) / f_max;
OSR = clock_in_etu / etu_divider;

temp = _BV(3) | (0x1UL << 4) | (databits - 1) & 0x3;
LPC_USART->LCR = temp | _BV(7);// databits&parity
LPC_USART->DLM = (system_clock_divider >> 8) & 0xff; // Fmax(Hi)
LPC_USART->DLL = system_clock_divider & 0xff; // Fmax(Low)
LPC_USART->FDR = (DivAddVal & 0x0F) | ((MulVal & 0x0F) << 4);// Fmax(Low)
LPC_USART->OSR = (OSR - 1) << 4; // Supesampling - Fi
LPC_USART->LCR &= ~(1 << 7); /* DLAB = 0 */
LPC_USART->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
LPC_USART->SCICTRL &= ~((0xffUL << 8) | (0x3UL << 5)); /* clear guard bits and retries */
LPC_USART->SCICTRL |= ((guardbits & 0xff) << 8) | /* guard bits */
((retries & 0x7) << 5); /* retries */
LPC_USART->IER = IER_RBR | IER_RLS; /* Enable UART interrupt */
}


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