Content originally posted in LPCWare by MrBool on Sat Jul 25 04:14:56 MST 2015
Thank you for reply.
In manual is "The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1])."
This equation is for bit rate. For example I have PCLK = 48MHz, CPSDVSR = 2 and SCR = 239.
This give me bit rate = 100kHz.
But what about timeout? How I can calculate it?