SGPIO + parallel interface

[lpcware]

Content originally posted in LPCWare by JMRouxel on Tue Jan 06 01:19:40 MST 2015
I'm working on the LP4350 part. I'm trying to use SGPIO to configure FPGA with parallel 8-bits data. It's the first time I try to use SGPIO and it seems a little confused for me for the moment.

So, to begin with SGPIO, I'm starting my tests from the following example : SGPIO_spi_master from the library lpc43xx.
This example emulates a SPI master (CLK, CS, MISO and MOSI). I can see the different signals on a scope (the clock for example).
My goal is to change the MOSI signal data (which is using just a SGPIO) to a parallel 8-bits data (with the use of 8 SGPIO)

First, when I modify the bits PARALLEL_MODE of the SLICE_MUX_CFG register (shift 1 bit per clock -> 1 byte per clock), I can't see the clock on my scope any more.
I assume that other parameters must be changed, but which?

Can anyone help me?

[atsuyosano]

I try a similar thing.
The output of parallel data 8bit and clk 1bit
Please tell me the register setting if I work well

[lpcware]

Content originally posted in LPCWare by JohnR on Thu Jan 08 07:47:59 MST 2015
Hi,

There is an SGPIO example that may be closer to what you are doing.

AN11343 SGPIO camera module design using LPC4300

From the text

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Quote:

The OV7670 is controlled via an I2C interface taking commands from LPC4300. Its output is a byte wide interface that sends out one byte per pixel clock. As each pixel is represented by 16 bits of data in an RGB565 format, it takes 2 pixel clocks from the camera to send out one pixel of image data

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I hope this helps
JohnR