SDRAM bank interleave

[lpcware]

Content originally posted in LPCWare by tvink on Tue Feb 24 06:49:34 MST 2015
Hi,

I am using a 64Mbit SDRAM that has 12 bit ROW addressing, 8 bit COL addressing, and it has 4 banks.

I am wondering what is the best way to connect the SDRAM's Bank address pins to the LPC1837. 

Also wondering what I should choose for address mapping in the LPC1837 "Dynamic Memory Configuration" registers.  I think my two choices area
1) 64Mb ( Row, Bank, Column )
or
2) 64Mb ( Bank, Row, column )


It seems that the 1st choice would promote interleaving... but does the EMC take care of that no matter which choice I make?

Does this choice affect the way the bank selects are wired to the LPC1837?

How should the bank selects be wired to the LPC1837 and which address mapping should I choose?


Thanks,
Tony

[lpcware]

Content originally posted in LPCWare by tvink on Tue Mar 17 05:49:40 MST 2015
Thanks...

I had read the app note.  However on the 3rd reading I did notice in table 1 that the SDRAM bank lines are supposed to be connected to pins EMC_A13:14.  So that answers one question. However I am still confused on programming the address mapping per table 365 in the user manual.  For my SDRAM my choices for "64Mb ( 4Mx16 ) 4 banks, row length=12, column length = 8" are ROW, BANK, COLUMN or BANK, ROW, COLUMN.

Does one choice promote interleave and one does not?
Which one?
Does this choice affect how the SDRAM is wired to the LPC18xx?

Thanks

[lpcware]

Content originally posted in LPCWare by bavarian on Tue Mar 17 04:51:40 MST 2015
Look into this application note:

http://www.lpcware.com/content/nxpfile/an11508-sdram-interface-lpc18xx43xx-emc

Regards,
NXP Support Team