Content originally posted in LPCWare by hiroto on Wed Sep 18 21:19:26 MST 2013
Hi iamzhangyong! and everyone!
I showing a result of the sample program on LPC2478 evaluation board (IAR LPC2478stk).
LPC2478 evaluation board is used by the mapping of 32bit SDRAM.
It's used two device(16bit SDRAM,K4S561632J-UC75x2) in fact.
I confirmed good working in this 32bit environment.
However, I confirmed the previous and similar problem at 16bit configuration.
I following the test results of three.
What's missing?
How to use to a (single) SDRAM(16bit) ?
case 1: Expected with EMCDYNAMICCONFIG0 = 0x4680(32bit)
case 2: Unexpeced with EMCDYNAMICCONFIG0 = 0x0680(16bit)
case 3: Expected if access length is short with EMCDYNAMICCONFIG0 = 0x0680(16bit)
Best Regards.
Hiroto
I describe in more detail below.
==========================================================
void SDRAM_Init (void)
{
// Assign pins to SDRAM controller
PINSEL5 &= BIN32(00000000,11111100,11111100,11000000);
PINSEL5 |= BIN32(01010101,00000001,00000001,00010101);
PINMODE5&= BIN32(00000000,11111100,11111100,11000000);
PINMODE5|= BIN32(10101010,00000010,00000010,00101010);
PINSEL6 = BIN32(01010101,01010101,01010101,01010101);
PINMODE6 = BIN32(10101010,10101010,10101010,10101010);
PINSEL7 = BIN32(01010101,01010101,01010101,01010101);
PINMODE7 = BIN32(10101010,10101010,10101010,10101010);
PINSEL8 &= BIN32(11000000,00000000,00000000,00000000);
PINSEL8 |= BIN32(00010101,01010101,01010101,01010101);
PINMODE8&= BIN32(11000000,00000000,00000000,00000000);
PINMODE8|= BIN32(00101010,10101010,10101010,10101010);
PINSEL9 &= BIN32(11111111,11110011,11111111,11111111);
PINSEL9 |= BIN32(00000000,00000100,00000000,00000000);
PINMODE9&= BIN32(11111111,11110011,11111111,11111111);
PINMODE9|= BIN32(00000000,00001000,00000000,00000000);
// Init SDRAM controller
// Enable EMC clock
PCONP_bit.PCEMC = 1;
EMCCONTROL = 1; // enable EMC
EMCDINAMICRDCFG = 1;
EMCDYNAMICRASCAS0_bit.CAS = 3;
EMCDYNAMICRASCAS0_bit.RAS = 3;
EMCDYNAMICRP = P2C(SDRAM_TRP); // SDRAM_TRP(20nS)
EMCDYNAMICRAS = P2C(SDRAM_TRAS); // SDRAM_TRAS(45nS)
EMCDYNAMICSREX = P2C(SDRAM_TXSR); // SDRAM_TXSR(67nS)
EMCDYNAMICAPR = SDRAM_TAPR; // SDRAM_TAPR(1)
EMCDYNAMICDAL = SDRAM_TDAL+P2C(SDRAM_TRP); // SDRAM_TDAL(3)+
EMCDYNAMICWR = SDRAM_TWR; // SDRAM_TWR(3)
EMCDYNAMICRC = P2C(SDRAM_TRC); // SDRAM_TRC(65nS)
EMCDYNAMICRFC = P2C(SDRAM_TRFC); // SDRAM_TRFC(66nS)
EMCDYNAMICXSR = P2C(SDRAM_TXSR); // SDRAM_TXSR(67nS)
EMCDYNAMICRRD = P2C(SDRAM_TRRD); // SDRAM_TRRD(15nS)
EMCDYNAMICMRD = SDRAM_TMRD; // SDRAM_TMRD(3)
//EMCDYNAMICCFG0 = 0x0000680; // 13 row, 9 - col, SDRAM
EMCDYNAMICCFG0 = 0x0004680;
// JEDEC General SDRAM Initialization Sequence
// DELAY to allow power and clocks to stabilize ~100 us
// NOP
EMCDINAMICCTRL = 0x0183;
for(volatile Int32U i = 200*30; i;i--);
// PALL
EMCDINAMICCTRL_bit.I = 2;
EMCDINAMICRFR = 1;
for(volatile Int32U i= 128; i; --i); // > 128 clk
EMCDINAMICRFR = P2C(SDRAM_REFRESH) >> 4;
// COMM
EMCDINAMICCTRL_bit.I = 1;
// Burst 4, Sequential, CAS-3
volatile unsigned long Dummy = *(volatile unsigned short *)
((Int32U)&SDRAM_BASE_ADDR + (0x32UL << (13)));
// NORM
EMCDINAMICCTRL = 0x0000;
EMCDYNAMICCFG0_bit.B = 1;
for(volatile Int32U i = 10000; i;i--);
}
void sdramtest()
{
unsigned char *ptr;
int dt = 1;
ptr = (unsigned char *)(0xa0000000);
for(int cnt=0;cnt<256;cnt++){ // 256bytes
*ptr++ = cnt;
}
}
---------------------------------------------------------------
case 1
Memory display after program execution(sdramtest) (32bit SDRAM mapping)
//EMCDYNAMICCFG0 = 0x0000680; // 13 row, 9 - col, SDRAM
EMCDYNAMICCFG0 = 0x0004680;
0xa0000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f <Expected
0xa0000010 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f <Expected
0xa0000020 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f <Expected
0xa0000030 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f <Expected
0xa0000040 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f <Expected
0xa0000050 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f <Expected
0xa0000060 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f <Expected
0xa0000070 70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f <Expected
0xa0000080 80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f <Expected
0xa0000090 90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f <Expected
0xa00000a0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af <Expected
0xa00000b0 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf <Expected
0xa00000c0 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf <Expected
0xa00000d0 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df <Expected
0xa00000e0 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef <Expected
0xa00000f0 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff <Expected
0xa0000100 80 81 ef fe 82 83 ff ff 84 85 ff ff 86 87 bf fb
---------------------------------------------------------------
case 2
Memory display after program execution(sdramtest) (16bit SDRAM mapping)
EMCDYNAMICCFG0 = 0x0000680; // 13 row, 9 - col, SDRAM
//EMCDYNAMICCFG0 = 0x0004680;
0xa0000000 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 00 01 02 03 <Unexpected
0xa0000010 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 10 11 12 13 <Unexpected
0xa0000020 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 20 21 22 23 <Unexpected
0xa0000030 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 30 31 32 33 <Unexpected
0xa0000040 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f <Unexpected
0xa0000050 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f <Unexpected
0xa0000060 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f <Unexpected
0xa0000070 70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f <Unexpected
0xa0000080 80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f <Unexpected
0xa0000090 90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f <Unexpected
0xa00000a0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af <Unexpected
0xa00000b0 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf <Unexpected
0xa00000c0 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf c0 c1 c2 c3 <Unexpected
0xa00000d0 d4 d5 d6 d7 d8 d9 da db dc dd de df d0 d1 d2 d3 <Unexpected
0xa00000e0 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef e0 e1 e2 e3 <Unexpected
0xa00000f0 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff f0 f1 f2 f3 <Unexpected
0xa0000100 ff ff ff f7 df ff 7f 9f fd fe ff ff df ff 7f ff <
---------------------------------------------------------------
case 3
void sdramtest()
{
unsigned char *ptr;
int dt = 1;
ptr = (unsigned char *)(0xa0000000);
for(int cnt=0;cnt<64;cnt++){ // 64bytes
*ptr++ = cnt;
}
}
-----------------------------------------------------------
Memory display after program execution(sdramtest) (16bit SDRAM mapping)
EMCDYNAMICCFG0 = 0x0000680; // 13 row, 9 - col, SDRAM
//EMCDYNAMICCFG0 = 0x0004680;
0xa0000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f <Expected
0xa0000010 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f <Expected
0xa0000020 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f <Expected
0xa0000030 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f <Expected
0xa0000040 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 40 41 42 43
-----------------------------------------------------
LPC2478-STK connection
SDRAM#1,#2 K4S561632J-UC75(16Mx16)x2
Row A0-A12
Col A0-A8
LPC2478 SDRAM#1 SDRAM#2
---------+-------------+-------------
A0 <-----> A0 <-----> A0
A1 <-----> A1 <-----> A1
A2 <-----> A2 <-----> A2
A3 <-----> A3 <-----> A3
A4 <-----> A4 <-----> A4
A5 <-----> A5 <-----> A5
A6 <-----> A6 <-----> A6
A7 <-----> A7 <-----> A7
A8 <-----> A8 <-----> A8
A9 <-----> A9 <-----> A9
A10 <-----> A10 <-----> A10
A11 <-----> A11 <-----> A11
A12 <-----> A12 <-----> A12
A13 <-----> BA0 <-----> BA0
A14 <-----> BA1 <-----> BA1
SDCLK <-----> CLK <-----> CLK
SDCLKEN<-----> CKE <-----> CKE
SDCS <-----> CS <-----> CS
SDWEN <-----> WE <-----> WE
CASN <-----> CAS <-----> CAS
RASN <-----> RAS <-----> RAS
DQMN0 <-----> DQML
DQMN1 <-----> DQMH
DQMN2 <------------------->DQML
DQMN3 <------------------->DQMH
D0 <-----> D0
D1 <-----> D1
D2 <-----> D2
D3 <-----> D3
D4 <-----> D4
D5 <-----> D5
D6 <-----> D6
D7 <-----> D7
D8 <-----> D8
D9 <-----> D9
D10 <-----> D10
D11 <-----> D11
D12 <-----> D12
D13 <-----> D13
D14 <-----> D14
D15 <-----> D15
D16 <------------------> D0
D17 <------------------> D1
D18 <------------------> D2
D19 <------------------> D3
D20 <------------------> D4
D21 <------------------> D5
D22 <------------------> D6
D23 <------------------> D7
D24 <------------------> D8
D25 <------------------> D9
D26 <------------------> D10
D27 <------------------> D11
D28 <------------------> D12
D29 <------------------> D13
D30 <------------------> D14
D31 <------------------> D15