Problems with CCAN BT configuration

[lpcware]

Content originally posted in LPCWare by dpliu on Mon Mar 25 23:50:29 MST 2013
the configurations which work well:
CAN PCLK=OSC=12MHz,CLKDIV=0,BT=0x2701(BRP=1),
means 500kbps*(2+7+3)*(BRP+1)=12MHz

the configurations which work with problems:
CAN PCLK=PLL1=204MHz,CLKIDV=0,BT=0x2721(BRP=33),
means 500kbps*(2+7+3)*(BRP+1)=204MHz

the configurations which also work with problems:
CAN PCLK=PLL1=204MHz,CLKIDV=5(CAN_CLK=PCLK/17),BT=0x2701(BRP=1),
means 500kbps*(2+7+3)*(BRP+1)=204MHz/17=12MHz

It seems there will be something wrong when use PLL1 as PCLK of CCAN.The CLKDIV(default 0) and the BRP(default 1) can only work with there default values? Or there are some strict order except INIT bit and CCE bit which I have known when configure the registers?

[lpcware]

Content originally posted in LPCWare by starblue on Fri Jan 31 02:29:23 MST 2014
In the LPC18xx user manual this has just been clarified:

* PCLK should be 50 MHz or less.

* The divisor is CLKDIVVAL + 1

(LPC18xx peripherals are mostly the same as LPC43xx).

[lpcware]

Content originally posted in LPCWare by starblue on Thu May 16 07:12:31 MST 2013
We also had trouble with CLKDIVVAL = 0 at 200 MHz, receiving a CAN message sometimes modified the setup of the message objects.  Maybe we were overclocking the C_CAN?

Our current working setup doesn't correspond to the 2^(CLKDIVVAL-1) + 1 values for the divisor in the user manual.
We get a divisor of 4 instead of 5 for CLKDIVVAL = 3.

In the C_CAN documentation for LPC11xx the divisor is specified as CLKDIVVAL + 1, which would fit.

Can someone from NXP clarify?