Missing JTAG TAP interface on one of my two LPC Link 2 boards! (Long Post)

[lpcware]

Content originally posted in LPCWare by fzfq3m on Thu Feb 13 18:45:16 MST 2014
Hi guys
I own two LPC Link 2 board and was trying to use one as debug adapter and the other as demo/target board, for two moths I've been trying to use either Openocd or Crossworks to connect in JTAG mode (CMSIS-DAP) both no luck so far... with Openocd it was a pain, the board sometimes refuses to connect and when it does then I'm unable to halt the processor, flash or just get info about the flash device... with rowley crossworks it always throws the error "Cannot set Debug Register"

Today while doing some test with help of rowley's support guys and I was able to detect that one of my board was having issues while being used as target board... to clarify:

I was using one LPC Link 2 as debug probe (let's call it DP board) and my second board as target (let's call it TD board); I've soldered a header on DP board (J6) and put a mark on TD board (painted NXP logo in blue) just to know which one is my debug probe and which one is my target... as per documentation available in the web I've been connecting the 10-pos IDC Ribbon Cable
from J7 on the DP board to J2 on the TD board.

My first try was to use Openocd with J-Link firmware but got some errors so I switched to CMSIS-DAP, I needed to compile a patched version of openocd (from it's gerrit code review server) because CMSIS-DAP support is still being tested... I got it working to some extent but to be honest I was fighting not only with the board but also with my lack of knowledge... I was never able to fully halt the processor (M0 was always refusing to halt) but sometimes I was able to even flash a blinky demo firmware to the board.

Since openocd gave me too many issues I tried Rowley Crossworks, but it only allowed me to connect using CMSIS-DAP in SWD mode... until for some reason I decided to try using an Olimex ARM-USB-OCD-H adapter with its AR-JATG 20-10 adapter... on both boards, and bingo! one of the board worked as expected!

Just to be sure I've downloaded LPCXpresso IDE and tried both boards confirming that one of them has issues! a JTAG TAP is missing!

please see the output of Openocd while using both board as target demo and olimex debug probe

The one that works (all three TAP found)
Open On-Chip Debugger 0.8.0-dev-00350-g6c74255 (2014-02-12-09:37)
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.sourceforge.net/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
adapter speed: 1000 kHz
cortex_m reset_config vectreset
Info : clock speed 1000 kHz
Info : JTAG tap: lpc4370.m4 tap/device found: 0x4ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x4)
Info : JTAG tap: lpc4370.m0sub tap/device found: 0x0ba01477 (mfg: 0x23b, part: 0xba01, ver: 0x0)
Info : JTAG tap: lpc4370.m0app tap/device found: 0x0ba01477 (mfg: 0x23b, part: 0xba01, ver: 0x0)
Info : lpc4370.m4: hardware has 6 breakpoints, 4 watchpoints
Info : lpc4370.m0sub: hardware has 2 breakpoints, 1 watchpoints
Info : lpc4370.m0app: hardware has 2 breakpoints, 1 watchpoints

The one that doesn't work (one M0 TAP missing)
Open On-Chip Debugger 0.8.0-dev-00350-g6c74255 (2014-02-12-09:37)
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.sourceforge.net/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
adapter speed: 1000 kHz
cortex_m reset_config vectreset
Info : clock speed 1000 kHz
Info : JTAG tap: lpc4370.m4 tap/device found: 0x4ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x4)
Info : JTAG tap: lpc4370.m0sub tap/device found: 0x0ba01477 (mfg: 0x23b, part: 0xba01, ver: 0x0)
Info : JTAG tap: lpc4370.m0app tap/device found: 0xffffffff (mfg: 0x7ff, part: 0xffff, ver: 0xf)
Warn : JTAG tap: lpc4370.m0app       UNEXPECTED: 0xffffffff (mfg: 0x7ff, part: 0xffff, ver: 0xf)
Error: JTAG tap: lpc4370.m0app  expected 1 of 1: 0x0ba01477 (mfg: 0x23b, part: 0xba01, ver: 0x0)
Error: Trying to use configured scan chain anyway...
Error: lpc4370.m0app: IR capture error; saw 0x0f not 0x01
Warn : Bypassing JTAG setup events due to errors
Warn : Invalid ACK 0x4 in JTAG-DP transaction

I also attached two images but this time using LPCXpresso, you can see that in one image only two TAP are reported

Now I'm not sure if the board came with this issue or if I the TAP interface was damaged/disabled while pplaying with openocd, but at this point I'm wondering if is there a way to save the board or if is lost
Thanks in advance and sorry for the long post!

[zhengyangqu]

I encountered the same problem, BUT I found things below very interesting. Look at OTP BANK0.

lpcscrypt.exe queryOTPMem

0x40045000 200000e0 00724f66 143905b3 00408187

0x40045010 00000000 00000000 00000000 00000000

0x40045020 00000000 00000000 00000000 00000000

0x40045030 20000080 00400000 00000000 00408000

0x40045040 00000000 00000000 00000000 00000000

0x40045050 83d9a706 9ec0e9d3 52ed8912 d44f2a3e

0x40045060 00000000 00000000 00000000 00000000

0x40045070 00000000 00000000 00000000 00000000

lpcscrypt.exe querypartdetailed

partID = 0x200000e0 0

decode = LPC43S70: - No Internal Flash

Core Clock = 180000000

Decoding: b100000000000000000000011100000

0:1 b00 USB0 USB2.0 HS

2:3 b00 USB1 USB2.0 HS (extern ULP)

4:6 b110 AES Capable

7 b1 CAN0 Disabled

8 b0 ETH Enabled

9 b0 LCD Enabled

10 b0 TURBO Capable

11 b0 M0sub Enabled

12 b0 M0app Enabled

13 b0 CAN1 Enabled

14 b0 SRAM_DATA 72KB at 0x10080000

15:16 b0 SRAM_CODE 128KB at 0x10000000

17 b0 SRAM_USB 32KB at 0x20000000

18 b0 SRAM_ETB 16KB at 0x2000c000

19 b0 SRAM_ETH 16KB at 0x20008000

20:26 Reserved

27 b0 EZH Enabled

28 b0 SGPIO Enabled

29 b1 M0sub_JTAG Disabled

30 b0 M0app_JTAG Enabled

31 b0 VADC Enabled

[lpcware]

Content originally posted in LPCWare by fzfq3m on Fri Mar 07 06:10:54 MST 2014

---

Quote: JohnR
Hi All,

Is there ay resolution to the question whether the LPC4370FET100 chip has two M0 processors?

In my application, I would like to use one M0 for data acquisition from an ADC, the M4 for data processing and the second M0 to drive a QVGA + touchscreen display.

Thanks for any help,

JohnR

---

Well, according to datasheet and user manual (UM10503) all LPC4370 are tripple core (1xM4 plus 2xM0), you can see in one of the attached images that there are three devices in the jtag chain (devices 1 and 2 are M0Sub and M0App respectively)

In my case I'm just having trouble with one of my board, the other board is working fine

Regards

[lpcware]

Content originally posted in LPCWare by nxpecosystem on Thu Mar 06 22:42:00 MST 2014
We'd like to take a look at your suspect LPC-Link2. I will contact you directly about how to return it to us.

[lpcware]

Content originally posted in LPCWare by JohnR on Thu Mar 06 12:31:31 MST 2014
Hi All,

Is there ay resolution to the question whether the LPC4370FET100 chip has two M0 processors?

In my application, I would like to use one M0 for data acquisition from an ADC, the M4 for data processing and the second M0 to drive a QVGA + touchscreen display.

Thanks for any help,

JohnR

[lpcware]

Content originally posted in LPCWare by fzfq3m on Fri Feb 21 09:41:29 MST 2014
I'll correct myself
I found that the TAP port IS disabled... on page 129 of UM10503 we can see info about CREG5 control register (address 0x40043118) were is possible to temporarily disable any of the available TAP interfaces by writing 1 to their respective control bit (bit 10 for M0SUBTAPSEL, bit 11 for M4TAPSEL and bit 12 for M0APPTAPSEL)...

Having a look at that register in my boards reveals that effectively the TAP interface for M0SUB in one of my board is disabled:
on the bad LPC4370 the CREG5 control register is set to 40000670 (1000000000000000000011001110000)
while on the good LPC4370  the CREG5 control register is set to 40000270 (1000000000000000000001001110000)

As you can see bit 10 on the bad lpc4370 is set to 1 which is why is disabled, the weird thing is that according to UM10503 this bits should be 0 after reset or power on but bit 10 is always set to 1. I even tried wrinting 0x40001E70 to that register (to disable all TAP intefaces) and after power cycling the board the CREG5 control register is set to 40000670 again.

Now apparently JTAG will be disabled by default when the AES Keys are programmed... so I need to do more research

Any comment will be appreciated

[lpcware]

Content originally posted in LPCWare by fzfq3m on Sat Feb 15 05:33:50 MST 2014
Thanks for the link

I couldn't find any info about disabled specific TAP interface on LPC4370 datasheet or cortex-m4 manual, so it is safe to assume that this is a silicon or marking error?

[lpcware]

Content originally posted in LPCWare by starblue on Fri Feb 14 06:15:12 MST 2014
You are not the first with this problem:

http://www.lpcware.com/content/forum/header-lpc4350-two-m0s

Don't let the title mislead you, it is about the LPC4370.

(BTW, the LPC4370 on my two LPC-Link2 are both triple-core, I just checked to make sure I'm not affected).

[lpcware]

Content originally posted in LPCWare by fzfq3m on Fri Feb 14 03:46:06 MST 2014
Well as far I can tell both mcu are LPC4370FET100
Both have following markings on mcu
LPC4370FET100
SYTK8             01
9SD12500CY

an on the back of the board I can read "Link 2-V3" on bottom copper layer so PCB are same I guess

[lpcware]

Content originally posted in LPCWare by lpcxpresso-support on Fri Feb 14 00:46:36 MST 2014
It looks like one of your cores is a 4370 (tri-core) and one is a 4350 (dual-core). You cannot make a dual-core into a tri-core....

Check the markings on the LPC device on the LPC-Link2.

I am not certain, but I think that LPC-Link2 has been built with both LPC4370 and LPC4350.