LPC55xx and Multi-channel Audio

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LPC55xx and Multi-channel Audio

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cdsteinkuehler
Contributor III

I need to implement a 4-in/4-out USB audio using an LPC5516.  I am working with the LPC55S16-EVK and started with the hid_audio_unified_freertos example.  This example has 2-in/2-out, but I was able to modify the audio playback logic based on the 5.1 example available as part of the audio_speaker example (and AN12939) to get more playback channels.

Now I need to get the additional audio data out via I2S, instead of just sending out 2 channels and dropping the rest of the data the way the audio_speaker example works.  This would be fairly easy if I could use the TDM mode and the extra channel pairs available with Flexcomm 6 & 7, but I need two separate data lines for I2S input and output (4 data lines total) to connect with my existing audio hardware which only supports I2S or Left-justified formats.

Are there any examples that demonstrate how to run multiple I2S Flexcomm channels in parallel using DMA?  I'm not worried about the I2S signal sharing (I've got that setup), I'm trying to figure out how to get DMA (and maybe interrupts) setup when running multiple channels in lock-step.  It seems like I would only want one interrupt and DMA callback for all channels, but I'm not seeing anything obvious in the SDK for I2S or the DMA that guarantees the channels will all start simultaneously if I'm enabling more than one channel.

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cdsteinkuehler
Contributor III

The I2S hardware has a DATAPAUSE bit which pauses data flow between the FIFO and the I2S (de)seralizer.  This feature is not supported by the SDK API, but the bit is directly addressable as I2S_CFG1_DATAPAUSE_SHIFT.

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

You said that you  need to implement a 4-in/4-out USB audio using an LPC5516,each FC module used as I2S can transfer two channels or more, you require two FC module for 4-in and two FC module for 4-out, you totally need 4 Fc modules. You can use ONE WS and ONE SCK signals to drive all 4 FC modules via Sys_ctrl module inter-connection.

BTW, The FC module used as I2S supports multiple slots in TDM mode, do your PCM stream have two slots(two channels) or multiple slots?

Regarding the DMA plus I2S, in SDK package, there is example

xiangjun_rong_0-1620293355181.png

 

This is the SDK link:

https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-s...

Hope it can help you

BR

XiangJun Rong

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cdsteinkuehler
Contributor III

I am familiar with the i2s_dma_transfer SDK example, but like the composite_hid_audio_unified example, it does not show multiple flexcomm channels being used for the same direction.  My PCM system only supports 2 slots per data line (I2S or Left-justified, as mentioned previously) so I need to "bond" two I2S flexcomm units together for each direction to support 4 audio channels.

I have setup the pin muxing and WS/SCLK sharing, but am unsure how to properly setup the DMA transfers so that both flexcomm channels start at the same time and stay in sync.

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cdsteinkuehler
Contributor III

The I2S hardware has a DATAPAUSE bit which pauses data flow between the FIFO and the I2S (de)seralizer.  This feature is not supported by the SDK API, but the bit is directly addressable as I2S_CFG1_DATAPAUSE_SHIFT.

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nclark
Contributor II

@cdsteinkuehler We are using LPC5526 in a similar fashion (2 Rx / 2 Tx I2S Flexcomms) and are finding that we have L/R channels swapping in one or more I2S Flexcomms. Is this something you experienced while working on this project? All of our I2S Flexcomms are acting as Slaves in this instance, and we are using the shared SCK and WS in SYSCTL. Thanks.

@rsk2 

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cdsteinkuehler
Contributor III

I didn't have any issues with left/right swapping but I am currently using 16-bit samples so each 32-bit word is one sample pair.

I did have a variety of very odd issues that turned out to be general lack of CPU performance when building the code in (the default) debug mode.  Switching to release builds generally fixed things.  If you're using 24 or 32 bit samples and are running out of CPU performance, I could see left and right getting occasionally swapped.

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nclark
Contributor II

Thanks for the reply, definitely very insightful! We are currently using 32-bit samples, but were considering trying 16-bit because we saw that the FIFO depth in particular was a bit small for 32-bit samples. We are seemingly processing data in an appropriate amount of time but, like you, thought there's a possibility that we are cutting it close.

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

I have checked the I2S_dma_transfer project, it uses two DMA channels, one is for transmitter, another is for receiver, you can follow up the code to add additional two FC module and add additional two DMA channels, it is okay.

Regarding the sync for two transmitter FC and two receiver FC modules, it is nothing to do with DMA if the DMA bandwidth is enough.

Hope it can help you

BR

Xiangjun Rong

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cdsteinkuehler
Contributor III

There are many examples showing DMA use for two channels in opposite directions.  I need to link two DMA channels moving data in the same direction to/from the same shared buffer.  I am asking if there are any examples or best practices for slaving multiple DMA channels while avoiding potential race conditions between interrupt service routines and during startup conditions/shutdown conditions.

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

Unfortunately, I have not the DMA linked example based on SDK package.

Pls try to refer to the thread.

https://community.nxp.com/t5/LPC-Microcontrollers-Knowledge/DMA-Ping-Pong-application/ta-p/1120977

Hope it can help you

BR

Xiangjun Rong

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