LPC55S69 - TPIU access

[hrainnie]

LPC55S69 --

Is it possible to read/write the TPIU space at 0xE0040000 from GDB?

I tried MCUXpresso 11 memory view and OpenOCD (my own hacked v8M version) and both of them bomb so badly the target needs a PoR.

Try:

x/x 0xE0040000

After that, the link is dead.

Is there a way to allow access to the TPIU? (I am trying to enable SWO for trace to trace an even more nasty CM33 double fault issue). Actually a set of reg/bit writes to enable SWO ITM would work fine too :smileyhappy:

tnx

Hedley

(Marvell Wireless group -> soon to be part of NXP).

GDB:
hrainnie@gravitar:/backup/NXP/trace/Debug$ arm-none-eabi-gdb spin.axf
GNU gdb (GNU Tools for Arm Embedded Processors 8-2018-q4-major) 8.2.50.20181213-git
(gdb) xyz0
0x00000000 in ?? ()
Only resetting the Cortex-M core, use a reset-init event handler to reset any peripherals or configure hardware srst support.
target halted due to debug-request, current mode: Thread
xPSR: 0x09000000 pc: 0x00000fea msp: 0x20043ff0
Loading section .text, size 0x3840 lma 0x20000000
Loading section .data, size 0x70 lma 0x20003840
Start address 0x2000016c, load size 14512
Transfer rate: 29 KB/sec, 7256 bytes/write.
Only resetting the Cortex-M core, use a reset-init event handler to reset any peripherals or configure hardware srst support.
target halted due to debug-request, current mode: Thread
xPSR: 0x09000000 pc: 0x00000fea msp: 0x20043ff0
(gdb) x/x 0xe0040000
0xe0040000: 0x00000000

OpenOCD:

root@gravitar:/usr/local/src/openocd-0.10.1/tcl# ../src/openocd -f board/lpc55xx.cfg
Open On-Chip Debugger 0.10.0
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
none separate
adapter speed: 500 kHz
cortex_mX3 reset_config vectreset
Info : CMSIS-DAP: SWD Supported
Info : CMSIS-DAP: JTAG Supported
Info : CMSIS-DAP: Interface Initialised (SWD)
Info : CMSIS-DAP: FW Version = 1.0
Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 1 TDO = 1 nTRST = 0 nRESET = 1
Info : CMSIS-DAP: Interface ready
Info : clock speed 500 kHz
Info : SWD DPIDR 0x6ba02477
Info : security extensions detected
Info : LPC5569.mX3: hardware has 8 breakpoints, 4 watchpoints
Info : accepting 'gdb' connection on tcp/3333
undefined debug reason 7 - target needs reset
Warn : Only resetting the Cortex-M core, use a reset-init event handler to reset any peripherals or configure hardware srst support.
target halted due to debug-request, current mode: Thread
xPSR: 0x09000000 pc: 0x00000fea msp: 0x20043ff0
Warn : Only resetting the Cortex-M core, use a reset-init event handler to reset any peripherals or configure hardware srst support.
target halted due to debug-request, current mode: Thread
xPSR: 0x09000000 pc: 0x00000fea msp: 0x20043ff0
Error: Failed to read memory and, additionally, failed to find out where
Polling target LPC5569.mX3 failed, trying to reexamine
Error: Could not initialize the debug port
Examination failed, GDB will be halted. Polling again in 100ms
Polling target LPC5569.mX3 failed, trying to reexamine
Error: Could not initialize the debug port
Examination failed, GDB will be halted. Polling again in 300ms
Polling target LPC5569.mX3 failed, trying to reexamine
^CError: Could not initialize the debug port
Examination failed, GDB will be halted. Polling again in 700ms

[xiangjun_rong]

Hi, Hedley,

As you know that the LPC55S69 only has SWD debug port, it does not have TRACE signals, so I suppose the LPC55S69 does not support TPIU function. The TPIU is optional module for M33 core.

BR

Xiangjun Rong

[hrainnie]

Hi Xiangjun,

Sure, no parallel trace/jtag.

That reg should return 0 if not implemented, not hang.

STs new cm33 stm32l522 also kills the debugger on that read.

Nordics new cm33 nRF5340 works. But it does support parallel trace.

You can crash the soc from non secure code with that read btw. Maybe a war would be for secure code to enable a fault region for that area. Not sure if the CPU will speculatively read that locn in parallel with the mpu check, so it might not work.#

Tnx

Hedley