LPC55S69 : CASPER and Core1

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LPC55S69 : CASPER and Core1

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Senior Contributor I

Hello !

In UM mentioned:

"

ARMv8-M architecture (ARM M33) introduces co-processor interface allowing CASPER
access via MCR (Move from Coprocessor to Register) and MRC (Move from Register to
Coprocessor) opcodes. Using this, up to two registers can be transferred between ARM
M33 core and CASPER.

"

If Casper act as coprocessor and Core1 dosn't supports coprocessors, it means CASPER can't be used from Core1 ?

Is this so ?

MPU, FPU, DSP, ETM, Trustzone (SECEXT), Secure Attribution Unit (SAU) or co-processor interface are not avaible on Core1.

What other peripherals can't be used from Core1 ?

What areas of SRAM are recommended for code execution for Core1 ?

Regards,

Eugene

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NXP TechSupport
NXP TechSupport

Hi Eugene

What do you mean " it means CASPER can't be used from Core1 "?

Casper is a accelerator engine. it's not a coprocessor.
Casper Sits on Cortex-M33 co-processor bus. An AHB bus and ARMv8-M Coprocessor (CP) interface to allow loading information to perform operations.
It works standalone from co-processor. Using CASPER can free up the ARM M33 to do other tasks while CASPER does the computation.

Fast shared RAM access 2x 32b RAMs which are allocated for CASPER RAM interface and shared with System Memory.

For Casper engine, I recommend a useful document:

https://www.nxp.com/docs/en/application-note/AN12445.pdf 

https://www.nxp.com/docs/en/application-note-software/AN12445SW.zip 


Have a great day,
Jun Zhang

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