Hello,
What is the recommended method to manually control the chip select when using the SPI bus? There doesn't appear to be an option to disable chip select control.
Thanks
Solved! Go to Solution.
Hi,
As the following SPI pins assignment, when you use FC3 as SPI master,
P0_7 FC3_RTS_SCLX_SSEL1
P0_8 FC3_SSEL3
When you configure the SPI3 control register to use the SSEL1, when you write data to SPI FIFOWR register, the FC3_RTS_SCLX_SSEL1 pin is driven to low by the spi module automatically, when the transfer is over, the pin will be driven to high automatically.
Of course, if you want to set/clear the FC3_RTS_SCLX_SSEL1 manually, as you know that the FC3_RTS_SCLX_SSEL1 is multiplexed with P0_7 pin, you can configure the P0_7 pin as GPIO, and configure it as GPIO output mode, before you write the FIFOWR register, clear the P0_7 pin by writting the GPIO output data register, after the transfer is over(you can use polling mode or interrupt mode to check the status register), you can set the P0_7 pin.
Hope it can help you
BR
XiangJun Rong
Hi,
As the following SPI pins assignment, when you use FC3 as SPI master,
P0_7 FC3_RTS_SCLX_SSEL1
P0_8 FC3_SSEL3
When you configure the SPI3 control register to use the SSEL1, when you write data to SPI FIFOWR register, the FC3_RTS_SCLX_SSEL1 pin is driven to low by the spi module automatically, when the transfer is over, the pin will be driven to high automatically.
Of course, if you want to set/clear the FC3_RTS_SCLX_SSEL1 manually, as you know that the FC3_RTS_SCLX_SSEL1 is multiplexed with P0_7 pin, you can configure the P0_7 pin as GPIO, and configure it as GPIO output mode, before you write the FIFOWR register, clear the P0_7 pin by writting the GPIO output data register, after the transfer is over(you can use polling mode or interrupt mode to check the status register), you can set the P0_7 pin.
Hope it can help you
BR
XiangJun Rong