LPC54113 Controller RAM

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 
已解决

LPC54113 Controller RAM

跳至解决方案
465 次查看
PK_1114
Contributor II

Dear Sir,

 

In the LPC54113 Controller RAM Area is erased by the software, Watchdog Reset time.

 

Thank You,

B Pavan Kumar

0 项奖励
回复
1 解答
452 次查看
xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

I suppose that there is not erasing concept for SRAM,you can write any data at any time to an address of SRAM. In  general, after reset, the data in SRAM is random, even if the data in SRAM are all zero, you can not take it for granted.

Hope it can help you

BR

XiangJun Rong

 

 

在原帖中查看解决方案

0 项奖励
回复
2 回复数
453 次查看
xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

I suppose that there is not erasing concept for SRAM,you can write any data at any time to an address of SRAM. In  general, after reset, the data in SRAM is random, even if the data in SRAM are all zero, you can not take it for granted.

Hope it can help you

BR

XiangJun Rong

 

 

0 项奖励
回复
446 次查看
frank_m
Senior Contributor III

To expand on that, SRAM is usually initialized in the startup code.
Most regions are cleared (to zero), others are initialized with constant data from Flash, according to the linker script settings.

If one want to change this behavior, this would be the place to implement it, i.e. the startup code in connection with the linker script and section definitions.

0 项奖励
回复