LPC43xx External Static Memory - Multiplexing of Address/Data lines

[lpcware]

Content originally posted in LPCWare by lochkartenman on Wed Oct 01 10:43:44 MST 2014
I would like to tightly-couple a FPGA with a µC by means of the external static memory memory controller, thereby effectively mapping the FPGA registers into main memory of the µC with maximum bandwidth. Possible candidates (amongst others?!) are the STM32F4xx and LPC43xx series, both with a 8/16/32-bit parallel External Static Memory Controller.

Of course these parallel interfaces require a lot of IOs (mostly address and data lines) and we are grateful for every pin we can spare.

The STM32 FSMC peripheral provides the ability to multiplex between address and data lines, which saves a lot of pins at the cost of only a single cycle. As far as I can tell, this ability is not mentioned in the LPC43xx datasheet/manual.

Am I missing something in the LPC43xx datasheet, or is this feature really only available in the STM32F4xx family?

[lpcware]

Content originally posted in LPCWare by lochkartenman on Thu Oct 02 02:31:02 MST 2014
Thanks for the clarification.

Regards,
Arne

[lpcware]

Content originally posted in LPCWare by bavarian on Thu Oct 02 02:20:57 MST 2014
Hello,

the external memory controller in our ARM7 and Cortex-M devices is an IP block from ARM which does not provide such a multiplexing feature.
That's maybe why ST calls their memory controller a "flexible memory controller". You can configure it to various operation modes.
Our EMC is more trimmed to higher speed and higher throughput, on the cost of flexibility and required number of pins.

Regards,
NXP Support Team.