I encountered the same problem as mentioned in this thread.
BUT I found something interesting. Hope someone can solve the problem.
Solved! Go to Solution.
According to this errata - 3.12 OTP.2, LPC4370 sometimes erroneously programs OTP memory. Some bits inside OTP will surely disable debug access to certain cores.
Should use special circuit to avoid this problem.
According to this errata - 3.12 OTP.2, LPC4370 sometimes erroneously programs OTP memory. Some bits inside OTP will surely disable debug access to certain cores.
Should use special circuit to avoid this problem.
Hi Zhengyang,
Do you modify the OTP area by yourself on our board?
From your post information, your 0x40045030 is 0x20000080, is it LE mode or BE mode? If BE mode, your JTAG_DISABLE bit is set, then the JTAG cann't be enabled by software and remains disabled.
Do you configure the OTP area by yourself?
Besides, do you try to use the Cortex M4 to read it, is it the same result?
Have a great day,
Kerry
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Thanks for your reply, Kerry.
Do you modify the OTP area by yourself on our board?
No, I was developing when finding M0SUB unaccessible.
is it LE mode?
Yes, it's LE mode, but 0x20000080 = 0b0010'0000'0000'0000'0000'0000'1000'0000 , bit31 is not set. but reserved bit 29 is set.
Do you configure the OTP area by yourself?
No.
Besides, do you try to use the Cortex M4 to read it, is it the same result?
Yes, I got this result with LPCScrypt software provided by NXP.
Besides, I found CREG5 is 0xc0000660 after reset. Bit 10 M0SUBTAPSEL is always set.
Hi Zhengyang Qu,
Thanks a lot for your updated information.
It's my mistake, yes, you are correct, if it is the LE mode, the JTAG_DISABLE bit is enabled.
I also check the OTP memory, this is my LPC-LINK2 information:
Yes, your JTAG_DISABLE is still enabled, about the reserved bit, we can ignore the data.
I have a question, if you the JLINK commander with SWD interface or JTAG interface, do you can connect your Cortext M4 core?
Have a great day,
Kerry
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Thanks for your reply, Kerry.
This is my result.
I have M4 and M0APP cores access.
PS: On another board with M0SUB core access, the result shows 3 JTAG taps can be detected. I think your LINK2 may have the same problem.