LPC4370 M0SUB core Jtag access accidentally disabled

[zhengyangqu]

I encountered the same problem as mentioned in this thread.

 BUT I found something interesting. Hope someone can solve the problem.

lpcscrypt.exe queryOTPMem

0x40045000 200000e0 00724f66 143905b3 00408187

0x40045010 00000000 00000000 00000000 00000000

0x40045020 00000000 00000000 00000000 00000000

0x40045030 20000080 00400000 00000000 00408000

0x40045040 00000000 00000000 00000000 00000000

0x40045050 83d9a706 9ec0e9d3 52ed8912 d44f2a3e

0x40045060 00000000 00000000 00000000 00000000

0x40045070 00000000 00000000 00000000 00000000

lpcscrypt.exe querypartdetailed

partID = 0x200000e0 0

decode = LPC43S70: - No Internal Flash

Core Clock = 180000000

Decoding: b100000000000000000000011100000

0:1 b00 USB0 USB2.0 HS

2:3 b00 USB1 USB2.0 HS (extern ULP)

4:6 b110 AES Capable

7 b1 CAN0 Disabled

8 b0 ETH Enabled

9 b0 LCD Enabled

10 b0 TURBO Capable

11 b0 M0sub Enabled

12 b0 M0app Enabled

13 b0 CAN1 Enabled

14 b0 SRAM_DATA 72KB at 0x10080000

15:16 b0 SRAM_CODE 128KB at 0x10000000

17 b0 SRAM_USB 32KB at 0x20000000

18 b0 SRAM_ETB 16KB at 0x2000c000

19 b0 SRAM_ETH 16KB at 0x20008000

20:26 Reserved

27 b0 EZH Enabled

28 b0 SGPIO Enabled

29 b1 M0sub_JTAG Disabled

30 b0 M0app_JTAG Enabled

31 b0 VADC Enabled

[zhengyangqu · Accepted solution]

According to this errata - 3.12 OTP.2, LPC4370 sometimes erroneously programs OTP memory. Some bits inside OTP will surely disable debug access to certain cores.

Should use special circuit to avoid this problem.

[kerryzhou]

Hi Zhengyang,

   Do you modify the OTP area by yourself on our board?

  From your post information, your 0x40045030 is  0x20000080, is it LE mode or BE mode? If BE mode, your JTAG_DISABLE bit is set, then the JTAG cann't be enabled by software and remains disabled.

Do you configure the OTP area by yourself?

Besides, do you try to use the Cortex M4 to read it, is it the same result?

Have a great day,
Kerry

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[zhengyangqu]

Thanks for your reply, Kerry.

Do you modify the OTP area by yourself on our board?

No, I was developing when finding M0SUB unaccessible.

is it LE mode?

Yes, it's LE mode, but 0x20000080 = 0b0010'0000'0000'0000'0000'0000'1000'0000 , bit31 is not set. but reserved bit 29 is set.

Do you configure the OTP area by yourself?

No.

Besides, do you try to use the Cortex M4 to read it, is it the same result?

Yes, I got this result with LPCScrypt software provided by NXP.

Besides, I found CREG5 is 0xc0000660 after reset. Bit 10 M0SUBTAPSEL is always set.

[kerryzhou]

Hi Zhengyang Qu,

    Thanks a lot for your updated information.

    It's my mistake, yes, you are correct, if it is the LE mode, the JTAG_DISABLE bit is enabled.

   I also check the OTP memory, this is my LPC-LINK2 information:

  Yes, your JTAG_DISABLE is still enabled, about the reserved bit, we can ignore the data.

  I have a question, if you the JLINK commander with SWD interface or JTAG interface, do you can connect your Cortext M4 core?

Have a great day,
Kerry

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[zhengyangqu]

Thanks for your reply, Kerry.

This is my result.

I have M4 and M0APP cores access.

PS: On another board with M0SUB core access, the result shows 3 JTAG taps can be detected. I think your LINK2 may have the same problem.