Content originally posted in LPCWare by bavarian on Thu Apr 07 02:55:30 MST 2016
For the LPC4357 flash device the normal boot order looks like this:
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[*] If valid content is found in internal flash bank #A, then it starts from there. "Valid" means in this case that at address 0x1A00001C there is a value which is the 2’s complement of the check-sum of the values in the 7 words before. See user manual UM10503 v2.0 chapter 6.4.4.1)
[*] If there is no valid flash content, the bootcode inspects the configuration of OTP bits and then the boot pins and selects the bootmode found there.
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This behavior can be changed by driving the ISP pin P2_7 to LOW during reset:
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[*] With valid or invalid code in flash bank #A, the boot loader checks the OTP bits and/or the external boot pins to determine the communication port. If the OTP bits and boot pins are set to USART0 or USART3, the part enters UART ISP mode.
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What happens if you have a program inside flash bank #A which then crashes?
Well, this can prevent you from getting access via JTAG, in order to reprogram the part. You need to know that the debugger also applies a reset to the chip, then wait for some period before trying to catch the core. If the crashing code sends the bus system and the core into Nirwana, somehow the JTAG access can fail. So please do the same as with a hardware reset: press and keep the ISP button and then start the debugger. Then the debugger reset is applied when P2_7 is low, the bootloader enters the ISP bootmode, therefore it does not start the faulty code and the JTAG access should work.
What helps during development is this:
Always add a long wait loop right at the beginning of your code (right after the assembler startup, beginning of C code) which keeps the core busy for let's say 2 seconds, then the debugger can catch the core there, before any code later on could cause any problems.
Regards,
NXP Support Team