[LPC4337] Synchronising SGPIO slices with LRCLK (I2S)

[lpcware]

Content originally posted in LPCWare by eva_lpc on Tue Aug 26 10:06:15 MST 2014
I'm trying to read in multiple I2S stereo-channels using SGPIO. The SCLK and LRCLK/WS are generated by the external AD-Converter. Every I2S stero-channel sends first 32 bits of one channel, when LRCLK is low, then 32 bits of the other channel when LRCLK is high. The data slices are shifted at the SCLK, which seems to go fine. After 32 bits, the slice buffers are swapped. So the data of the first channel should be in one buffer, and data of the second channel in the other buffer.  However I need to align the data with the LRCLK/WS, so that the 32 bits in one buffer are the actual 32 bits of the corresponding channel. Now there are offsets resulting in mixed up data in the buffers.

How can I synchronise the slices with this LRCLK? I cannot use LRCLK as qualifier as I also need the data the is sent when LRCLK is low.

[lpcware]

Content originally posted in LPCWare by eva_lpc on Fri Aug 29 01:51:12 MST 2014
Right now I am synchronising by waiting inline for a match of "0xFFFFFFFF" on the LRCLK. When a match is detected I immediately turn on all other slices. It works for LRCLK frequencies < 100kHz. If LRCLK > 100kHz apparently the slices are not turned on quick enough because the first bit of the next word is clocked in as the last bit, so there is a offset.

It is fine for now as I do not need sample frequencies higher than 100kHz, but if there is a more elegant solution that always works, please let me know.

[lpcware]

Content originally posted in LPCWare by starblue on Wed Aug 27 01:19:13 MST 2014
You could use two slices per channel, with opposite polarity qualifiers (unless you have too many channels).

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