Content originally posted in LPCWare by starblue on Thu Apr 16 06:35:31 MST 2015
Quote: SteveO
I have discovered it is possible to write and read back as high as IPR15. IPR16 and higher do not seem to be implemented.
Yes, interrupts are implemented in groups of 32 (mostly). There is a register ICTR which tells you how many groups there are, see "ARM v7-M Architecture Reference Manual" DDI0403.
And from "The Definitive Guide to ARM Cortex -M3 and Cortex-M4 Processors", 3rd Edition by Joseph Yiu:
"you can obtain the exact number of interrupts available by writing to interrupt control registers such as interrupt enable/pending registers while the PRIMASK register is set (to disable the interrupt from taking place), and read back to see exactly how many bits are implemented in the interrupt enable/pending registers."