LPC1788 EMC timing registers settings

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LPC1788 EMC timing registers settings

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aut
Contributor I

Hi all.

I have the following system: uP LPC1788, external DRAM IS42S32160F_7TLI,  7" touch screen display. I'm having strange behaviors. Randomly, the system doesn't start or it starts but after many minutes or hours, it stops (crashes) with strange display screen. I don't have idea about the problem. Certainly no hard fault occurs. Can be a DRAM reset (zeroing)?
I think I followed the correct DRAM initialization but I have some doubts about it. The EMC clock is set to 60MHz. The refresh time indicated by DRAM dataheet is 64ms, the DRAM rows number is 8192 so I set the DYNAMICREFRESH register to 0x1B that is, the interval refresh between two rows is 7.2us. Is this correct? Another doubt concerns, in general, the timing settings when the DRAM works at a frequency lower than the maximum indicated in the data sheet. For example, the IS42S32160F_7TLI maximum frequency value is 143MHz. For this frequency, the DRAM datasheet indicate a minimum tRAS equal to 42ns corresponding to 6 clock cycle. My question is: if the DRAM works at frequency lower than 143MHz, for example 60 MHz, the tRAS time has to be set greather than 100ns (6 clock cycle of the 60MHz) or greater than 42ns? I have done the tRAS example but the same question applies for all timing registers. In general it is correct to refer to clock cycles or times?

Many thanks 

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