I am not sure what am I doing wrong, but ssel0 never gets pulled low. I am using lpcxpresso1549 board with arduino ethernet shield. Pins are configured in SWM as per arduino requirement.
P0.12 - MISO
P0.28 - Mosi
P0.14 - SCK
P0.27 - SSEL0
Checking PINASSIGN3 and 4, shows correct assignment. I left IOCON as default.
SPI0 is enabled, TXCTL->SEL0 = 1, rest are 0.
CFG->SPOL0 = 0; CFG->MASTER = 1; CFG->CPHA = 0; CFG->CPOL = 0;
SYSCON->SYSAHBCLKCTRL1->SPI0 = 1
Starting spi0 write, ssel never gets low.
SPI->STAT->RXRDY = 1; TXRDY = 1; STALLED = 1; SSA = 1; ENDTRANSFER = 0; IDLE = 0;
If I control the ssel pin manually I get some garbage on the clock and master out (not what I would expect to get), also after burst of 8bits spi0 status go to stalled.
The logic in TXDATCTL that controls the SSEL pins is inverted, so bit 16 (TXSSEL0) should be 0 and bits 17-19 (TXSSEL1 to TXSSEL3) should be 1.
Hello Sven Savic ,
Recommend you first refer to the SPi demo under LPCopen:
LPCOpen Software for LPC15XX | NXP
Have a great day,
TIC
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Ok, I have checked the sample code and it works on the same shield. What I have noticed in the sample code is that it is setting IOCON for pins in undocumented way ??
#define IOCON_DIGMODE_EN (0x1 << 7) /*!< Enables digital function (analog pins only) */ Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 27, (IOCON_MODE_INACT | IOCON_DIGMODE_EN));
In the documentation 7th bit is defined as reserved while in the code it is set to digital mode enable. Which one is correct ?
Hello Sven,
Both are right, you can see the Reset value of bit 7 is 1, so there is no matter whether config like code.
Have a great day,
TIC
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