Hitex LPC1850 evaluation board------reconfig SPIFI speed and lpc18xx-2013-09-04[1].zip

[lpcware]

Content originally posted in LPCWare by robert on Fri Dec 06 01:17:13 MST 2013
Dears,

Now we use the Hitex LPC1850 evaluation board: LPC1850FET256P6G566.04 ESD11460AY, and SPANSION FL064P1F 1059030. We find there is two problem:
1.use the NXP 2012-06 level-II training code:HOT7_SPIFI, if we reconfig the SPIFI colock, when simulate and debug, the MCU will entry HardFault_Handler; when run in SPI Flash, will dead, maybe also entry HardFault_Handler. Why?  SPI flash problem, or library or ROM code/library compatibility ?

2.download the lpc18xx-2013-09-04[1].zip code, use uart polling example code, then find the Baud rate is not right, becaue the pc receive date is messy code. why?

Thanks and Best regards
Robert

[lpcware]

Content originally posted in LPCWare by mc on Mon Dec 16 10:43:00 MST 2013
Hi Robert,
You can debug the reason of hard fault. Go to
Peripheral Menu -> Core Peripheral -> Fault Reports

After this you will see the register as in  the attached PNG file.

If you still can not debug Please post your project here.

[lpcware]

Content originally posted in LPCWare by robert on Wed Dec 11 19:44:32 MST 2013
Dear MC,

Yes , i run the code in RAM.

[lpcware]

Content originally posted in LPCWare by mc on Wed Dec 11 07:46:23 MST 2013
Hi Robert,
Please run routine from RAM which are modifying SPIFI clock (QSPI clock). Changing SPIFI clock while executing from QSPI flash will create problems.

[lpcware]

Content originally posted in LPCWare by robert on Sun Dec 08 19:50:22 MST 2013
Hi MC,

KEIL.

Thanks.

[lpcware]

Content originally posted in LPCWare by mc on Fri Dec 06 15:47:00 MST 2013
Hi Robert,
Which IDE are you using? Let me know I will post the code.

Thanks,
MC