Content originally posted in LPCWare by devel@latke.net on Mon Aug 12 09:54:12 MST 2013
Answering myself.
The very responsive (as in, responding on a Saturday to a question posed on a Friday night!) NXP team tells me that, no the EMC when used to talk to static devices is asynchronous and the relationship between the EMC address/data/control signals and an EMC_CLK cannot be guaranteed.
The obvious solution is to use the standard synchronizing techniques in the FPGA, and to make sure that the chip select and read/write timings are such that everything is recognized properly in the FPGA clock domain.
Having said that ... this doesn't make any sense, because the EMC bus is synchronized to something in the processor, and the provisions for clock outputs to handle SDRAM are in place, so why not support a non-burst non-dynamic-memory synchronous bus mode? That should be EASY.
Of course, the Atmel memory bus seems to have the same limitation, so I expect that it's an ARM IP issue and not an NXP issue.
Thanks.