Content originally posted in LPCWare by [email protected] on Wed Aug 07 12:39:28 MST 2013 I am in the process of choosing an ARM device for a project which requires High Speed USB and also includes an FPGA. LPC18xx looks promising.
Can the EMC be used as a synchronous bus interface to my FPGA? I see that there is a note in the data sheet about "Synchronous static memory devices (synchronous burst mode) are not supported." I don't need a burst mode.
I guess my questions are when the EMC is configured to work as a static external memory interface, with accesses in one of the four static-memory chip select address ranges:
Can I use one of the EMC_CLK signals for my FPGA clock, or are they only available if a dynamic interface is enabled?
If so, then are the various EMC signals (EMC_A[], EMC_WE, EMC_OE, EMC_CS, EMC_D) synchronous to that clock?
Content originally posted in LPCWare by [email protected] on Thu Aug 15 21:46:39 MST 2013 Quote: mdittrich I am doing a similar thing, it works, but there are caveats:
You may have to enable and then not use a dynamic CS, there is a bit in the dynamic memory configuration that keeps the clocks going constantly. I have SDRAM on my board, so I have not tried using a clock with static memory only.
Thanks for the info!
The double-read-cycles thing is interesting, especially the part about If you look in the user manual, chapter 19.7.21, Register StaticConfig, Bit "B" (Buffer Enable): there is a hint [2] "EMC may perform burst read access even when the buffer enable bit is cleared because the data sheet takes great pains to say that the async static EMC interface doesn't do burst access! The advice in that thread to use an LPC17xx part is well-considered but I need High Speed USB.
I figured that at the least, I would enable a dynamic address space and as you say, just not use it. I don't expect to need SDRAM as the on-chip RAM should suffice, and if I need more memory, I can map FPGA BRAM into one of the static chip-select spaces too.
I ordered one of the kits so I can do some tests to see how the bus access actually works.
Content originally posted in LPCWare by [email protected] on Mon Aug 12 09:54:12 MST 2013 Answering myself.
The very responsive (as in, responding on a Saturday to a question posed on a Friday night!) NXP team tells me that, no the EMC when used to talk to static devices is asynchronous and the relationship between the EMC address/data/control signals and an EMC_CLK cannot be guaranteed.
The obvious solution is to use the standard synchronizing techniques in the FPGA, and to make sure that the chip select and read/write timings are such that everything is recognized properly in the FPGA clock domain.
Having said that ... this doesn't make any sense, because the EMC bus is synchronized to something in the processor, and the provisions for clock outputs to handle SDRAM are in place, so why not support a non-burst non-dynamic-memory synchronous bus mode? That should be EASY.
Of course, the Atmel memory bus seems to have the same limitation, so I expect that it's an ARM IP issue and not an NXP issue.
You may have to enable and then not use a dynamic CS, there is a bit in the dynamic memory configuration that keeps the clocks going constantly. I have SDRAM on my board, so I have not tried using a clock with static memory only.
