DMA cacheable, bufferable?

[lpcware]

Content originally posted in LPCWare by rockyh on Mon Oct 06 10:41:41 MST 2014
Hi,
I don't feel I have a good understanding of the "Cacheable" and "Bufferable" bits with regards to the LPC43xx DMA controller. The User Guide just mentions these options, but does not go into any detail, and I also cannot find any appnote that explains them. Can anybody explain what these options do?
Thanks

[lpcware]

Content originally posted in LPCWare by Pacman on Mon Oct 06 21:40:15 MST 2014
...And cahe... would probably be a pretty bad idea to use with GPIO pins. ;)
-You'd end up receiving wrong information if you did that.

[lpcware]

Content originally posted in LPCWare by mch0 on Mon Oct 06 12:22:09 MST 2014
Hi,

looks like these two bits define the bus access type that is generated on the AHB.
Whether the peripheral actually uses this information is a good question, though.

Bufferable would indicate that the write does not have to "go through" to the final destination immediately.

One target that could use this information is the EMC, particularly the SDRAM interface.
The SDRAM controller has local buffers for each of the four regions (see UM 22.8.4).
However, the write policy does not seem to be influenced by the "bufferable" information provided by the DMA.
It more or less seems to follow its own agenda acting like a mini-cache.

Since the UM is so sparse on information, I'd actually assume that this information has no influence whatsoever on the transaction(s) to any peripheral or bridge.

But I'm guessing here,

Mike