My target is K60 mask 1N30D. I am developing an application that spends most of the time waiting for external event. While waiting for event the micro should be put in VLLS3 and when wakened up the application must continue from the same point where it was put to sleep. The VLLS3 wakeup goes through a reset so I do the following: save all the relevant registers (i.e. CPU, NVIC, peripheral registers etc) to RAM, configure VLLS3 and perform WFI instruction. On reset I recognize LLWU wakeup, switch to alternate stack, restore all the saved registers, restore saved stack pointer and branch to the instruction next to WFI. Everything works fine. The problem comes I am trying to integrate this stuff to OS scheduler, i.e. when the scheduler can’t find any task able to run, it should put the micro to sleep. The problem is that the scheduler runs in PendSV ISR context. If I branch back to ISR code and load EXC_RETURN value to PC, the CPU tries to fetch instruction from address 0xfffffff9 instead of performing exception return sequence. Ok, so I figured out that in order to return from exception I need to enter to exception first, so when I detect LLWU wakeup, the PendSV is activated, everything is restored, the code jumps to instruction next to WFI and finally does POP PC (LR was pushed to stack at the ISR beginning). Now I am getting usage fault with INVPC bit set… The stack looks just right including LR, PC and XPSR values. I went over “Integrity checks on exception return” chapter in ARM v7m reference manual, all conditions seems to be satisfied and I am stuck. Does anyone tried to do something similar? Any thoughts and advices will be greatly appreciated.
