arm cortex m0+ interrupts enable/disable

[alexleonte]

Hi,

I was wondering what is the difference between this two methods for disabling interrupts

1.CPSID causes interrupts to be disabled by setting PRIMASK.

2.Disable all Device-specific interrupts writing in NVIC->ICER[0] + Disable System exceptions (example SysTick - timer and interrupt)

Thx,

[jeremyzhou · Accepted solution]

Hi Alex,

During the initial reset, NVIC is turned off. Therefore, the processor cannot receive any interrupts (except for NMI, Reset interrupt, and hard fault). To turn on the interrupts with configurable priority:

asm volatile ("cpsie i");

“CPSIE I” is a assembly instruction to enable the priority configurable interrupts. Actually, it’s a shortcut to this longer procedure.

1 2	asm volatile ("MOVS r0, #0\n\ MSR PRIMASK, r0");

To turn off the priority configurable interrupts:

asm volatile ("cpsid i");

Or, taking the longer non-atomic procedure:

1 2	asm volatile ("MOVS r0, #1\n\ MSR PRIMASK, r0");

And the NVIC is applicable to enable or disable specific interrupt, the only thing that you need to do is to set IRQ X ‘Set Enable Register’ (ISER) or ‘Clear Enable Register’ (ICER).

Please learn more information about it through the link as below.

ARM Information Center

Hope this helps.
Have a great day,
Ping

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[pizzburg]

This answer is useful. I'm workong on KEA128 with a M0+ core.  

The processer core funciton " __disable_irq"  and  "__get_CONTROL " cannot turn off or turn on interrupts.

But this asm work!     __asm volatile ("cpsie i");    

Solved my problem. 

__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}

__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;

__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}