UART FLUSH

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UART FLUSH

2,870 Views
pascalschröer
Contributor V

Hi at all,

my problem is to flush the RX FIFO of the UART module (MK10DX128VLH7). I don't know

why the FIFO isn't empty if I do the flush command.

The Function:

The PC sends two Bytes to the uC. For example "0x1111" or "0x2222". Depending on this command,

the uC should do some different things, until there is a stop command. For example "0x3333".

This function works very well!

My problem is to capture a fault command or a command which is sent out with the wrong baud rate.

In this case, I would like to do a RX FLUSH command and wait for the next "interpretable" command.

The UART Initialisation:

SIM_SCGC4 |= SIM_SCGC4_UART1_MASK;

UART1_C2  = 0x00;                                                                          // Turn the UART module off

UART1_RWFIFO = 0x02;                                                                 // Set the RX FIFO TDRE flag to 2Bytes

UART1_TWFIFO = 0x02;                                                                 // Set the TX FIFO TDRE flag to 2Bytes                                 

UART1_PFIFO |= UART_PFIFO_RXFE_MASK;                             // Enable the RX FIFO

UART1_PFIFO |= UART_PFIFO_TXFE_MASK;                             // Enable the TX FIFO

UART1_CFIFO |= UART_CFIFO_RXFLUSH_MASK;                    // FLUSH the RX FIFO (initialisation)

UART1_CFIFO |= UART_CFIFO_TXFLUSH_MASK;                    // FLUSH the TX FIFO (initialisation)

// Set the BUAD RATE

UART1_BDH = baud_rate_tmp>>8;

UART1_BDL = baud_rate_tmp;

UART1_C4   = 0x00

                        | BFRA_tmp;         

UART1_C2  = 0x00

                       |UART_C2_TE_MASK                                            // Enable Transmitter

                       |UART_C2_RE_MASK;                                          // Enable Receiver

INTERRUPT_CONFIG(UART1_IRQ,interrupt_en,3);                    /* Initialize the interrupt */

The UART Interrupt:


void UART1_isr(void)

{

  uint16_t rxd_tmp = 0;                                                                     /* Temporary receive variable */   

  if ((UART1_S1&UART_S1_RDRF_MASK) >= 1)                           /* Check if the Receive Data Register Full Flag is set */

  {

     rxd_tmp |=  UART1_D;

     rxd_tmp = rxd_tmp<<8;

     rxd_tmp |=  UART1_D;

    

      UART1_CFIFO |= UART_CFIFO_RXFLUSH_MASK;                    //That doesn't work!

     switch(rxd_tmp)

     {

       case COMMAND1:

                 State = 1;

       break;

       case COMMAND2:

                 State = 2;

       break;

       case COMMAND3:

                 State = 3;

       break;

       default:

       break;

     }

  }

}

Thank you!

Pascal

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1,321 Views
Kan_Li
NXP TechSupport
NXP TechSupport

Hi Pascal,

How did you figure out that the FIFO is not empty after you did the flush operation? Would you please help to clarify?

BTW, The RM recommends disable TE or RE before doing the flush operation, Please kindly refer to the following for more details.

1.png


Have a great day,
Kan

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1,321 Views
pascalschröer
Contributor V

Thanks for your answer!

Now, I have solved the problem. The problem was to "believe" in the debugger-register-view...

Have a nice day!

BTW: You were right, I have to clear the RE bit before performing the flush command!

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