Hi Puspam Nayak,
Actually whether parallel terminations to VTT are required for the address and control signals and also whether series terminations are needed for all of the signals (including data) is very board dependent.
On the tower board TWR-K70F120M we have the DDR2 placed very close to the processor. In order to put parallel terminations on the address and control lines we would have to route the signals to the top or bottom layer of the board in order to make a connection to a surface mount resistor. Because we didn’t include the parallel terminations we actually have a cleaner layout with shorter traces and less vias on the lines.
Another factor is the speed. We run the DDR2 with a max clock of 150MHz, but the minimum clock frequency for DDR2 spec is 125MHz. So we are just barely running the memory above its minimum speed, and address and command line operate at clock rate so half of the data rate – therefore termination is less critical than the ODT part(data lines), for your case , to interface single DDR2, so signal grouping will be easy and trace lengths will be extremely short if you put DDR2 close to processor as well as TWR-K70F120M does. This last point is important because impedance matching and related reflection problems are less and less relevant while lengths shorten. so this makes it easier for us to run the memory without using the parallel/serial terminations, because we don’t require the super fast transition times on the signals.
Actually Customers will have to make their own determination on whether they can design their boards the same way. The safest route is to include the parallel terminations, but that does complicate routing and add components to the board.
Hope that helps,
Have a great day,
Kan
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