Problems with the meaning of Flash Clock and Bus Clock

[zhitailiu]

Hi, just got my first lovely FRDM-KV10Z board.

I have some question about the clocks. Hope you guys don't mind this is my first time using Cortex MX.

The maximal allowed settings:

Core Clock = System Clock = 75Mhz.

Flash/Bus clock (the same here in KV10Z) = 25MHz

This seems to be wired for me. 

Does that mean the arm core can run in 75MHz, but the instruction fetching speed is only up to 25MHz??

Or at least the core is in wait state most of the time?

I made a simple test, using system tick module to count how many system ticks past during some instruction. 

For example, 50 __NOP()  instructions took about 80 system ticks.

This made me even more confused, I suppose 3 system ticks will execute one instruction.

However, this is good news for I originally supposed that it would take about 150 system ticks due to the core/bus clock ration.

Can anyone make some explanation about this?

How can I estimate the instruction fetching speed, and make sure that the core is not in wait state?

Do I misunderstand something about this?

Thanks for reading this post!

[egoodii · Accepted solution]

First and foremost the flash is 2 instructions wide.  For this particular test, 50 instructions is 25 fetches, or 1us.  In said 1us are 75 core-ticks.  Cortex-M is 'Thumb instruction set', optimized at 16bits.

The flash-interface-system also has some fetch/'cache' helpers to improve flash-execute performance.  Many instructions will involve access-cycles to 'non Flash', like RAM/Stack and peripherals, so 'real work' will better-fill the CPU time than a linear sequence of NOPs.  That all being said, for truly 'execution speed critical' operations you might benefit running those routines in RAM (look for the best RAM-block to put that in, maybe with consideration for where your stack is).

[zhitailiu]

Great thanks!
Now I got it!