PLL locking

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PLL locking

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Contributor I

Hi, all

My question is about PLL locking:

I work with CORTEX K70 and our card design is a bit different from evaluation board ( "Tower").

We work from internal clock and use oscillator 1 and PLL1 instead of oscillator 0.

Sometimes PLL stay not locked in despite of lock bit setting (MCG  S2 register) or , may be, losses  it.

Did you have similar problem and how did you solve it?

Thanks

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NXP TechSupport
NXP TechSupport

Hello Mira,

As Mark mentioned above, I was wondering if you can clarify what exact purpose you want to achieve.

Looking forward to your reply.
Have a great day,
Ping

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Specialist V

Hello Mira

Coud you please explain the exact configuration that you use? You mention that you work with the internal clock and configure PLL1 but not what speeds are used for oscillator, PLL and what they are driving. Where does MCGOUTCLK come from?

Below is am image of the K70's MCG with some additional register controls shown - which switches are set and which maths are valid?

Note that the external 32kHz oscillator is required to transition to using PLL1 as MCGOUTCLK, in case that is an aim.

I have worked with PLL0 and PLL1  from Oscillators 0 and 1 without any issues so if you detect loss of clock try also feeding the oscillator in question with an clock singnal rather than crystal to see whether the crystal circuit is a cause of difficulties.

Regards

Mark

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