I2C Start Detect Possible with MKL15Z128VFT4 Arm M0 Processor

[jonathan_guinta]

Hi,

I'm in the midst of working on a test head system where I have one I2C master and up to 21 slave addresses on an I2C bus. I've noticed the IAAS bit gets set in the I2Cx_S I2C Status Register when data is sent on the I2C bus no matter whether it occurs directly after a start condition (slave address condition) or embedded in data later in the stream. I've pulled up a scope to check the SCLK and SDA lines and do not appear to have a glitch condition occurring for the Start and Stop conditions (they appear to be in the right spots). Does any one have any suggestions/remedies for this? I noticed there's a Start byte in the reserved addresses for the I2C specification, is this for the purpose of uC's that are not able to accommodate this (detecting the Start condition)? Please let me know what I'm doing wrong here. I just want the uC to be able to differentiate between data and a slave address based on where in the stream the byte falls with respect to the start condition.

Thanks!

Jon

[Kan_Li]

Hi Jonathan,

The IAAS bit is set by one of the following conditions:

• The calling address matches the programmed primary slave address in the A1 register, or matches

the range address in the RA register (which must be set to a nonzero value and under the condition

I2C_C2[RMEN] = 1).

• C2[GCAEN] is set and a general call is received.

• SMB[SIICAEN] is set and the calling address matches the second programmed slave address.

• ALERTEN is set and an SMBus alert response address is received

• RMEN is set and an address is received that is within the range between the values of the A1 and

RA registers.

Please kindly help to check if you meet either of them. Thanks for your patience!

Have a great day,
Kan

NXP Technical Support
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