We use the MKV31F256VLH12 controller from NXP in a new design.
Programming takes place via the SWD interface.
Programmer: J-Link Plus from Segger.
Also an external watchdog with an open drain output is provided
in the circuit.
The watchdog output is separted over a 470R Resistor from the Reset Pin of the
controller.
The watchdog currently forces a reset approx. Every 400ms.
Unfortunately also during the programming cycle.
Is there a possibility that the programmer (J-Link Plus) keeps the RESET signal permanently high while the controller is being programmed?
A jumper between the output of the watchdog and the reset pin of the controller is not an option (lost / forgotten).
best regards
Helmut
解決済! 解決策の投稿を見る。
Hello,
Meanwhile I have a solution. The Segger Programmer doesn`t need a connection to the Reset Pin
during the programming cycle. In the textfixture for programming and test we connect the reset pin of the Controller with Vdd during the programming cycle. Then the watchdog has no chance to reset
the controller.
After some consideration, I wasn’t able to come up with a viable option to do this given the limitations.
Perhaps the Segger support team could have a better insight on how to achieve this.
Regards,
Edwin.
Hello,
Meanwhile I have a solution. The Segger Programmer doesn`t need a connection to the Reset Pin
during the programming cycle. In the textfixture for programming and test we connect the reset pin of the Controller with Vdd during the programming cycle. Then the watchdog has no chance to reset
the controller.