Hello,
You can check in the Cortex M0+ :
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0484c/DDI0484C_cortex_m0p_r0p1_trm.pdf
AIRCRa Application Interrupt and Reset Control Register in the ARMv6-M Architecture ReferenceManual.
Checking in the ARMv6-M RM :
In the AIRCR register, WO - SYSRESETREQ bit. : Writing 1 to this bit asserts a signal to request a reset by the external system.
This register is in address : 0xE000ED0C
So you should write the bit [2] SYSRESETREQ in that address to request a SW reset. Take care with the rest of the bits value, modify only that bit.
Regards,
Luis
Hello,
You can check in the Cortex M0+ :
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0484c/DDI0484C_cortex_m0p_r0p1_trm.pdf
AIRCRa Application Interrupt and Reset Control Register in the ARMv6-M Architecture ReferenceManual.
Checking in the ARMv6-M RM :
In the AIRCR register, WO - SYSRESETREQ bit. : Writing 1 to this bit asserts a signal to request a reset by the external system.
This register is in address : 0xE000ED0C
So you should write the bit [2] SYSRESETREQ in that address to request a SW reset. Take care with the rest of the bits value, modify only that bit.
Regards,
Luis