LPUART on K66F

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a8Chcx
Contributor V

Hi,

I am going to use LPUART on K66F and tried the sample code in SDK. I have the following questions:

From sample code:

BOARD_InitPins();

BOARD_BootClockRUN();

CLOCK_SetLpuartClock(1U);

/*

* config.baudRate_Bps = 115200U;

* config.parityMode = kLPUART_ParityDisabled;

* config.stopBitCount = kLPUART_OneStopBit;

* config.txFifoWatermark = 0;

* config.rxFifoWatermark = 0;

* config.enableTx = false;

* config.enableRx = false;

*/

LPUART_GetDefaultConfig(&config);

config.baudRate_Bps = BOARD_DEBUG_UART_BAUDRATE;

config.enableTx = true;

config.enableRx = true;

LPUART_Init(DEMO_LPUART, &config, DEMO_LPUART_CLK_FREQ);

// For clock setting...

const sim_clock_config_t simConfig_BOARD_BootClockRUN =

{

.pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */

.pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */

.pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */

.er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */

.clkdiv1 = 0x1140000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /5 */

};

Based on the above sample code, the input clock for LPUART is 120MHz instead of 60MHz(Max frequency allowed for LPUART based on document).

Could you tell me if it is right? Should I change pllFllDiv to 1 to make it 60MHz for LPUART?

Thanks,

Christie

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839件の閲覧回数
mjbcswitzerland
Specialist V

Hello Christie

That is why I asked, because I was not aware of an "official" limitation in the LPUART's clock speed.
The user's manual specifies that that it uses the bus clock and also its own LPUART clock (which needs to remain enabled when in a low power mode that still uses the LPUART operation). Although the LPUART is clocked from its own clock for operation I suspect that the bus clock is mentioned because it is used for accessing the LPUART registers by the CPU.

I have attached a FRDM-K66F binary that uses your settings and communicates on PTE8 and PTE9 (available on headers J37 and J38) with 120MHz system clock, 60MHz bus clock and the LPUART from MCGPLLCLK at 120MHz (no divides), which shown normal operation (it is using DMA for efficiency).

This corresponds to your test configuration and has a command line menu for simpler testing the interface.

In addition there are indications that the LPUART operates asynchronously to the bus clock. In any case I know of nothing stating that 120MHz is not allowed. Practically however, if there is no reason to have 120MHz as clock and a slower frequency (eg. divide by 5 from MCGPLLCLK) is adequate I would chose a slower one to reduce current consumption. I have also attached a binary which is using MCGPLLCLK/5 (24MHz) which is also fine for 115.2kBaud (allows 115'384 Baud).

If you change the divider you may also need to inform the UART configuration routines accordingly/manually so that they calculate the Baud values correctly.

I can build these using the uTasker project without any complications since it automates all details (no matter what processor, UART type or interface) but if you base work on example snippets you may need to co-ordinate things to ensure they don't break when not using them in their example form and may need different examples to be able to use on different chips and such.

Regards

Mark

Complete Kinetis K66 solutions, training and support:  http://www.utasker.com/kinetis.html
Kinetis K66:
- http://www.utasker.com/kinetis/TWR-K65F180M.html
- http://www.utasker.com/kinetis/FRDM-K66F.html
- http://www.utasker.com/kinetis/TEENSY_3.6.html

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840件の閲覧回数
mjbcswitzerland
Specialist V

Hi Christie

Could you specify in which document the 60MHz LPUART limitation is specified since I find it neither in the latest data sheet nor the latest user's manual.

Thanks

Regards

Mark

Complete Kinetis K66 solutions, training and support:  http://www.utasker.com/kinetis.html
Kinetis K66:
- http://www.utasker.com/kinetis/TWR-K65F180M.html
- http://www.utasker.com/kinetis/FRDM-K66F.html
- http://www.utasker.com/kinetis/TEENSY_3.6.html

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a8Chcx
Contributor V

Hi Mark,

It said in K66F reference manual in table:

LPUART0--->Bus clock

But, it didn't say it is max clock for LPUART0. Can I use 120MHz(MCGPLLCLK) for LPUART0?

Thanks,

Christie

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840件の閲覧回数
mjbcswitzerland
Specialist V

Hello Christie

That is why I asked, because I was not aware of an "official" limitation in the LPUART's clock speed.
The user's manual specifies that that it uses the bus clock and also its own LPUART clock (which needs to remain enabled when in a low power mode that still uses the LPUART operation). Although the LPUART is clocked from its own clock for operation I suspect that the bus clock is mentioned because it is used for accessing the LPUART registers by the CPU.

I have attached a FRDM-K66F binary that uses your settings and communicates on PTE8 and PTE9 (available on headers J37 and J38) with 120MHz system clock, 60MHz bus clock and the LPUART from MCGPLLCLK at 120MHz (no divides), which shown normal operation (it is using DMA for efficiency).

This corresponds to your test configuration and has a command line menu for simpler testing the interface.

In addition there are indications that the LPUART operates asynchronously to the bus clock. In any case I know of nothing stating that 120MHz is not allowed. Practically however, if there is no reason to have 120MHz as clock and a slower frequency (eg. divide by 5 from MCGPLLCLK) is adequate I would chose a slower one to reduce current consumption. I have also attached a binary which is using MCGPLLCLK/5 (24MHz) which is also fine for 115.2kBaud (allows 115'384 Baud).

If you change the divider you may also need to inform the UART configuration routines accordingly/manually so that they calculate the Baud values correctly.

I can build these using the uTasker project without any complications since it automates all details (no matter what processor, UART type or interface) but if you base work on example snippets you may need to co-ordinate things to ensure they don't break when not using them in their example form and may need different examples to be able to use on different chips and such.

Regards

Mark

Complete Kinetis K66 solutions, training and support:  http://www.utasker.com/kinetis.html
Kinetis K66:
- http://www.utasker.com/kinetis/TWR-K65F180M.html
- http://www.utasker.com/kinetis/FRDM-K66F.html
- http://www.utasker.com/kinetis/TEENSY_3.6.html

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a8Chcx
Contributor V

Thanks. I am going to lower input clock of LPUART...

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