Kinetis DMAMUX Errata Clarification Sought

[hexman]

Hi, in the Errata 1N86B, Section e4588: DMAMUX: When using PIT with "always enabled", there is mentioned a workaround involving mysterious "DMASREQ=channel". Could you, please, explain what it means (e.g. any DMAMUX or DMA register(s) like DMA_SERQ, and the corresponding value(s))? Thanks.

[mjbcswitzerland]

Hi

I don't use the PIT like this so didn't need to use the workaround but I am 99% sure that it just means

DMA_TCDn_CSR |= DMA_TCD_CSR_DREQ;

DMAMUX_CHCFGn &= ~(DMAMUX_CHCFG_ENBL);

DMAMUX_CHCFGn |=  DMAMUX_CHCFG_ENBL;

Whereby the DMAMUX_CHCFGn register has a 6 bit DMA channel source (slot) which I think is being referred to by "DMASREQ=channel". In fact I don't know which channel number is entered initially when using the periodic triggering function (maybe it doesn't matter?).

As I understand the errata, the PIT can still be used to trigger a single major loop operation of 1 but then requires the interrupt to be handled. If the minor loop count is also 1 it then requires an interrupt for each DMA transfer, which would cancel much of the DMA operation benefit. If there is still a free FTM module or the LPTMR available these could possibly be used instead of PITs(?) to trigger DMA.

Regards

Mark

[hexman · Accepted solution]

Hi Mark,

finally got time to check this. It seems that the DMASREQ is a typo and actually means the DMA_SERQ register with its DMA channel enable bits. Additionally, without the clearing and re-enabling the ENBL bit in DMAMUX0_CHCFGn, the PIT trigger will be simply ignored and the DMA channel will work totally unimpeded.

However, I got a different code for the DREQ bit. I set it BEFORE the very first start/activation of the DMA channel. Also in the DMA DONE interrupt I re-enable the automatically cleared DMA request enable bit ERQn in the DMA_ERQ register. Without re-enabling the ERQn, the DMA channel will simply stop. Asking the Freescale engineers, please, have a look at this!

// enable DREQ and major loop interrupt BEFORE any DMA channel action

DMA_TCDn_CSR = DMA_CSR_DREQ_MASK | DMA_CSR_INTMAJOR_MASK;

// DMAn interrupt handler

void DMAn_ISR (void) {

  DMA_CINT = DMA_CINT_CINT(n); // clear DMAn INTn flag

  // deassert DMAn request workaround

  DMAMUX0_CHCFGn &= ~DMAMUX_CHCFG_ENBL_MASK; // clear ENBL

  DMAMUX0_CHCFGn |=  DMAMUX_CHCFG_ENBL_MASK; // set ENBL

  DMA_SERQ = DMA_SERQ_SERQ(n); // re-enable DMAn request enable bit (set ERQn bit in DMA_ERQ)

}

[jeremyzhou]

Hi Hexman,

Thank you very much for your focus on Freescale Kinetis product. I'm glad to provide service for you.

I've taked your Service Request:1-1850625733. I was also a little confused with the meaning of "DMASREQ=channel" after had a brief look through the Errata 1N86B.

However I think the DMASREQ is doc error and it should be SERQ in DMA_SERQ register after I reviewed it again.

About the workaround, the difference between your workaround and the workaround provided in the Errata 1N86B 's the location of set the DMA_TCDn_CSR[DREQ] bit.

In my opinion, both methods are ok and you could try these both methods.

I'm looking forward your test result.
Have a great day,
Ping

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[hexman]

Hi Jeremy,

According to my tests, setting the DREQ bit only in the DMAn interrupt service routine will allow the DMAn channel to immediately restart one or more times until the CPU handles the DMAn interrupt and finally sets the DREQ bit.

On the contrary, when the DREQ bit is set BEFORE any DMAn action, the DMAn channel correctly stops right after the first pass (major loop completed).

So I will stick to my solution. The Errata 1N86B needs to be corrected.

Best regards,

Hexman

[jeremyzhou]

Hi Hexman,

Thanks for your reply.

I was wondering if you could upload your code, then I could test this code too.

I promise I will update you immediately when I get the test result and report this issue if the test result just like your description.
Have a great day,
Ping

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