KV5x nano-edge with deadtime?

[arimendes]

Hi,

I would like to know if is possible to have nano-edge placement on a complementary output and with deadtime insertion on the KV5x.

If I Initialize the pwm as complementary with a deadtime, it works ok. If I enable the nano-edge for PWM_A, the nano-edge works and the PWM_B stays as complementary of PWM_A but without deatime.

Ari.

[arimendes]

Xiangjun Rong,

Thanks for your help. It is working know.

without fractional delays: DTCNT0 = DEADTIME; and DTCNT1 = DEADTIME.

with fractional delays: DTCNT0 = DEADTIME<<5; and DTCNT1 = DEADTIME<<5.

Ari.

[xiangjun_rong · Accepted solution]

Hi, Ari,

Pls read the following part, the DTCNT0 field is dependent on whether you use fractional mode, if you do not use fractional mode, the Low 11 bits represent the delay which is counted by the IP_Bus lcoks. If you use fractional mode, you should left shifts 5 bits, because the low 5 bits in  PWMx_SMnDTCNT0 represent the fractional dead time delay of IP-BUS lock.

Pls refer to section 48.4.23 Deadtime Count Register 0 (PWMx_SMnDTCNT0) in RM of KV5x.

Hope it can help you.

BR

Xiangjun Rong

The DTCNT0 field is interpreted differently depending on whether or not the fractional delays are being
used (FRCNTRL[FRAC23_EN] is set). If the fractional delays are off, then the upper 5 bits of DTCNT0 are
ignored and the remaining 11 bits are used to specify the number of cycles of deadtime. In this case the
maximum value is 0x07FF which indicates 2047 cycles of deadtime. If the fractional delays are being
used, then the upper 11 bits of DTCNT0 represent the number of whole cycles of deadtime and the lower
5 bits of each register represent the fractional cycle added to the whole number. In this case the maximum
value is 0xFFFF which represents 2047 31/32 cycles of deadtime.
The DTCNT0 field is used to control the deadtime during 0 to 1 transitions of the PWM_A output
(assuming normal polarity).