KEA128 FTM input capture,single channel

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KEA128 FTM input capture,single channel

761 次查看
ID7729
Contributor I

I want to use FTM2ch3 of KEA128 to achieve PWM wave duty cycle capture.However, the frequency band that can be captured is very limited, too low frequency PWM wave can not be captured, I would like to ask you have met the same situation.The code is as follows:

void init_FTM(void) {
SIM_SCGC |= SIM_SCGC_FTM2_MASK;/* Sys Clk Gate Ctrl: enable bus clock to FTM1,2 */
 
/* FTM2 module settings for desired channel modes: */
FTM2_MODE |= FTM_MODE_WPDIS_MASK; /* Write protect to registers disabled (default) */
FTM2_COMBINE = 0x00000000; /* DECAPEN (Dual Edge Capture Mode Enable) = 0  */
/* COMBINE (chans n & n+1) = 0 (default; independent chans) */
 
FTM2_MOD = 0xFFFF;
FTM2_CNTIN = 0x01;
FTM2_SC = 0x07; /* CWMS (Center aligned PWM Select) = 0 (default, up count) */
/* TOIE (Timer Overflow Interrupt Ena) = 0 (default) */
/* CLKS (Clock source) = 0 (default, no clock; FTM disabled) */
/* PS (Prescaler factor) = 7. Prescaler = 2**7 = 128 */
}
 
void init_FTM2_ch3_IC(void) {
FTM2_C3SC = 0x48; /* FTM2 ch3: Input Capture on falling edge */
/* CHIE (Chan Interrupt Ena) = 0 (default) */
/* MSB:MSA (chan Mode Select) = 0b00 */
/* ELSB:ELSA (chan Edge or Level Select) = 0b01 */
SIM_PINSEL1 &= ~SIM_PINSEL1_FTM2PS3_MASK;
}
 
void start_FTM_counters(void) {
FTM2_SC |= FTM_SC_CLKS(1); /* Start FTM2 ctr with clk source TIMER_CLK (20 MHz)*/
}
 
void FTM2_IRQHandler(void)
{
FTM2_C3SC &= ~FTM_CnSC_CHF_MASK;
if(flag == 0)
{
CurrentCaptureVal1 = FTM2_C3V;
FTM2_C3SC = 0x00000048; /* FTM2 ch3: Input Capture on falling edge */
/* CHIE (Chan Interrupt Ena) = 1 (default) */
/* MSB:MSA (chan Mode Select) = 0b00 */
/* ELSB:ELSA (chan Edge or Level Select) = 0b10 */
flag = 1;
FTM2_CNT = 0x00000001;
}
else
{
CurrentCaptureVal2 = FTM2_C3V;
FTM2_C3SC = 0x00000044; /* FTM2 ch3: Input Capture on rising edge */
/* CHIE (Chan Interrupt Ena) = 1 (default) */
/* MSB:MSA (chan Mode Select) = 0b00 */
/* ELSB:ELSA (chan Edge or Level Select) = 0b01 */
flag = 0;
}
}
 
int main(void) {
 
  init_clks_FEE_40MHz(); /* KEA128 clks FEE, 8MHz xtal: core 40 MHz, bus 20MHz */
 
   init_FTM ();              /* Enable bus clock to FTM1,2 prescaled by 128 */
   init_FTM2_ch3_IC();         /* PTB5 input; connect J2_5 and J2_10  */   
NVIC_EnableIRQ(FTM2_IRQn);
    start_FTM_counters();
 
for (;;) {}
}
 
Can you help me?
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ID7729
Contributor I

Hi Miguel,

Thanks for your reply. My target frequency is 100Hz.In my program, I set up two global variables, which allows me to receive the counter value in

time. I use the monitoring window to monitor them. I found that only the frequency is greater than 3KHz, the counter value will be stable.

At 100Hz, the two global variables change very fast, it is extremely unstable. And I have calculated that the value of CNT does not overflow.

So I'm confused.

Thank you for your help.

Best Regards, ID7729.

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Miguel04
NXP TechSupport
NXP TechSupport

Hi @ID7729 

You have the channel configurated to capture on rising edges, have you tried to use it in rising and falling edges? 

Refer to AN5142 chapter 3.8:

"When ELSnB:ELSnA=11, the mode is Capture on rising/falling edge, the mode is used to test duty
cycle."

Best Regards, Miguel.

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Miguel04
NXP TechSupport
NXP TechSupport

Hi @ID7729 

The input frequency should not be causing the problem, since the input capture counts from rising, falling or rising and falling edges. 

The reference manual only specifys that it has a maximum frquency not a minimum.

26.4.4 Input Capture mode

Note that the maximum frequency for the channel input signal to be detected correctly is system clock divided by 4, which is required to meet Nyquist criteria for signal sampling.

Can you tell me the frquency you are measuring?

Best Regards, Miguel.

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