K60 as SPI slave, questions regarding SS, PUSHR_SLAVE, ISR

[fzhao614482]

I need to write code to make the K60 as a SPI slave device, and it must behave a certain way. I have a few questions

Is it possible to assign a rising or falling edge interrupt to the slave select pin if its alternate function is configured to be the slave select pin? I need to know if I can use an event handler before the first byte is transfered. I need to know how to process incoming data in my transmit complete interrupt according to whether or not it was the first byte of the entire transaction.

SPIx_PUSHR_SLAVE is 32 bits, if I set my frame size to 8 bits, and I put in 0xA1B2C3D4 into SPIx_PUSHR_SLAVE , and 8 bits are shifted out, then I write 0x12345678 into SPIx_PUSHR_SLAVE, then the master shifts another 8 bits, then the master has received 0xD4 and then 0x78, correct?

What if I set my frame size to 8 bits, and I put in 0xA1B2C3D4 into SPIx_PUSHR_SLAVE once, and 8 bits are shifted out twice by the master, would the master has received 0xD4 and them 0xD4? Or would it receive 0xD4 and then 0xC3?

Is there a timing diagram that will show me the latency between the bits being transfered and the occurance of the transmit complete interrupt?

Does anybody have a SPI slave example implementation or driver/library/module that they can share?

[yumbrad]

These questions are interesting to me as well. I had a working slave setup on SPI2, and when I switched it to SPI0, transmitting data broke. I have a setup where a master wiggles the clock for 10 bytes - sending two bytes initially which the slave acts on and replies to in the next 8 bytes - for the below example, the master should receive 0x0 0x0 H E L L O K 6 0. The slave always receives the master's 2 bytes ok.

If I run (not debug) the internal flash config from Codewarrior, it doesn't drain the TXFIFO - it transmits ok  in the third byte, but only the first byte I ever load into the tx push register. (The master receives 0x0 0x0 H H H H H H H H)

If I instead hard reset to run, it drains the TXFIFO, but the response is delayed by a byte - the master receives three "zero" bytes instead of two. (The master receives 0x0 0x0 0x0 H E L L O K 6)

Any ideas on this? Again, it was working on SPI2. I'll attach the code I'm using - hopefully this can help fzhao or others.

[hansonhe]

Do you have any update about this problem?

[gogreen]

Hi yumbrad,

I'm a novice programmer for K60.

Can you please provide a sample code or an application note for SPI2 (master and slave) interface on TWR-K60? (uTasker code didn't help me)

I'm using IAR v6.3, atleast please provide some material for SPI2 communication.

- GoGreen

[stav]

I have a similiar problem - I am writing code for a K40. The SPI is configured as an 8 bit slave. A stream of bytes is sent intermittently to chip. The  slave sends between 2 and 8 bytes one at a time (ie the fifo is loaded and the byte sent before the next byte is loaded). I find that the slave gets stuck on the first byte that is sent - it repeatedly sends only that byte, and nothing affects this. I am using SPI2 for this.

[Muffinman]

You need read the data out before you can send the next data. (it is full deplex even it works at half duplex.).

[yumbrad]

btw - in the attachment, the difference in the RSER register between my SPI0 and SPI2 init was an experiment - it works/doesn't work the same way if SPI0_RSER is init'd to 0x00020000.